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features ? high performance, low power avr ? 32 uc 32-bit microcontroller ? compact single-cycle risc instruction set including dsp instruction set ? read-modify-write instructions and atomic bit manipulation ? performing 1.49 dmips / mhz up to 91 dmips running at 66 mhz from flash (1 wait-state) up to 49 dmips running at 33 mhz from flash (0 wait-state) ? memory protection unit ? multi-hierarchy bus system ? high-performance data transfers on separate buses for increased performance ? 15 peripheral dma channels improves speed for peripheral communication ? internal high-speed flash ? 512k bytes, 256k bytes, 128k bytes versions ? single cycle access up to 33 mhz ? prefetch buffer optimizing instru ction execution at maximum speed ? 4ms page programming time and 8ms full-chip erase time ? 100,000 write cycles, 15-year data retention capability ? flash security locks and us er defined configuration area ? internal high-speed sram, si ngle-cycle access at full speed ? 64k bytes (512kb and 256kb flash), 32k bytes (128kb flash) ? external memory interface on at32uc3a0 derivatives ? sdram / sram compatible memory bus (16-bit data and 24-bit address buses) ? interrupt controller ? autovectored low latency interrupt service with programmable priority ? system functions ? power and clock manager including inte rnal rc clock and one 32khz oscillator ? two multipurpose oscillators and tw o phase-lock-loop (pll) allowing independant cpu frequency from usb frequency ? watchdog timer, real-time clock timer ? universal serial bus (usb) ? device 2.0 full speed and on-the-go (otg) low speed and full speed ? flexible end-point configuration and management with dedicated dma channels ? on-chip transceivers including pull-ups ? ethernet mac 10/100 mbps interface ? 802.3 ethernet me dia access controller ? supports media independent interf ace (mii) and reduced mii (rmii) ? one three-channel 16-b it timer/counter (tc) ? three external clock inputs, pwm, capture and various counting capabilities ? one 7-channel 16-bit pulse width modulation controller (pwm) ? four universal synchronous/asynchro nous receiver/transmitters (usart) ? independant baudrate generator, suppo rt for spi, irda and iso7816 interfaces ? support for hardware handshaki ng, rs485 interfaces and modem line ? two master/slave serial peripheral inte rfaces (spi) with chip select signals ? one synchronous serial protocol controller ? supports i2s and generic frame-based protocols ? one master/slave two-wire interfa ce (twi), 400kbit/s i2c-compatible ? one 8-channel 10-bit anal og-to-digital converter ? 16-bit stereo audio bitstream ? sample rate up to 50 khz 32058fs?avr32?08/08 avr ? 32 32-bit microcontroller at32uc3a0512 at32uc3a0256 at32uc3a0128 at32uc3a1512 at32uc3a1256 at32uc3a1128 preliminary summary
2 32058fs?avr32?08/08 at32uc3a ? on-chip debug system (jtag interface) ? nexus class 2+, runtime control, non-intrusive data and program trace ? 100-pin tqfp (69 gpio pins), 144-pin lqfp (109 gpio pins) ? 5v input tolerant i/os ? single 3.3v power supply or dual 1.8v-3.3v power supply
3 32058fs?avr32?08/08 at32uc3a 1. description the at32uc3a is a complete system-on-chip microcontroller based on the avr32 uc risc processor running at frequencies up to 66 mhz. avr32 uc is a high-performance 32-bit risc microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on low power consumption, high code density and high performance. the processor implements a memory protection unit (mpu) and a fast and flexible interrupt con- troller for supporting modern operating systems and real-time operating systems. higher computation capabilities ar e achievable using a rich set of dsp instructions. the at32uc3a incorporates on-chip flash and sram memories for secure and fast access. for applications requiring additional memory, an external memory interface is provided on at32uc3a0 derivatives. the peripheral direct memory access controlle r (pdca) enables data transfers between periph- erals and memories without processor involv ement. pdca drastically reduces processing overhead when transferring continuous and la rge data streams between modules within the mcu. the powermanager improves design flexibility and security: the on-chip brown-out detector monitors the power supply, the cpu runs from t he on-chip rc oscillator or from one of external oscillator sources, a real-time clock and its associated timer keeps track of the time. the timer/counter includes three identical 16- bit timer/counter channels. each channel can be independently programmed to perform frequency measurement, event counting, interval mea- surement, pulse generation, delay timing and pulse width modulation. the pwm modules provides seven independent channels with many configuration options including polarity, edge alignment and waveform non overlap control. one pwm channel can trigger adc conversions for more accurate close loop control implementations. the at32uc3a also features many communication interfaces for communication intensive applications. in addition to standard serial interfaces like uart, spi or twi, other interfaces like flexible synchronous serial controller, usb and ethernet mac are available. the synchronous serial controller provides easy access to serial communication protocols and audio standards like i2s. the full-speed usb 2.0 device interface supports several usb classes at the same time thanks to the rich end-point configuration. t he on-the-go (otg) host interface allows device like a usb flash disk or a usb printer to be directly connected to the processor. the media-independent interface (mii) and reduced mii (rmii) 10/100 ethernet mac module provides on-chip solutions for network-connected devices. at32uc3a integrates a class 2+ nexus 2.0 on-chip debug (ocd) system, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control.
4 32058fs?avr32?08/08 at32uc3a 2. configuration summary the table below lists all at32uc3a memory and package configurations: 3. abbreviations ? gclk: power manager generic clock ? gpio: general purpose input/output ? hsb: high speed bus ? mpu: memory protection unit ? ocd: on chip debug ? pb: peripheral bus ? pdca: peripheral direct memory access controller (pdc) version a ? usbb: usb on-the-go controller version b device flash sram ext. bus interface ethernet mac package at32uc3a0512 512 kbytes 64 kbytes yes yes 144 lead lqfp at32uc3a0256 256 kbytes 64 kbytes yes yes 144 lead lqfp at32uc3a0128 128 kbytes 32 kbytes yes yes 144 lead lqfp at32uc3a1512 512 kbytes 64 kbytes no yes 100 lead tqfp at32uc3a1256 256 kbytes 64 kbytes no yes 100 lead tqfp at32uc3a1128 128 kbytes 32 kbytes no yes 100 lead tqfp
5 32058fs?avr32?08/08 at32uc3a 4. blockdiagram figure 4-1. blockdiagram uc cpu nexus class 2+ ocd instr interface data interface timer/counter interrupt controller real time counter peripheral dma controller 512 kb flash hsb-pb bridge b hsb-pb bridge a memory interface s mm m m m s s s s s m external interrupt controller high speed bus matrix fast gpio general purpose ios 64 kb sram general purpose ios pa pb pc px a[2..0] b[2..0] clk[2..0] extint[7..0] kps[7..0] nmi_n gclk[3..0] xin32 xout32 xin0 xout0 pa pb pc px reset_n external bus interface (sdram & static memory controller) cas ras sda10 sdck sdcke sdcs0 sdwe ncs[3..0] nrd nwait nwe0 data[15..0] usb interface dma id vbof vbus d- d+ ethernet mac dma 32 khz osc 115 khz rcosc osc0 pll0 pulse width modulation controller serial peripheral interface 0/1 two-wire interface pdc pdc pdc miso, mosi npcs[3..1] pwm[6..0] scl sda usart1 pdc rxd txd clk rts, cts dsr, dtr, dcd, ri usart0 usart2 usart3 pdc rxd txd clk rts, cts synchronous serial controller pdc tx_clock, tx_frame_sync rx_data tx_data rx_clock, rx_frame_sync analog to digital converter pdc ad[7..0] advref watchdog timer xin1 xout1 osc1 pll1 sck jtag interface mcko mdo[5..0] mseo[1..0] evti_n evto_n tck tdo tdi tms power manager reset controller addr[23..0] sleep controller clock controller clock generator col, crs, rxd[3..0], rx_clk, rx_dv, rx_er mdc, txd[3..0], tx_clk, tx_en, tx_er, speed mdio flash controller configuration registers bus memory protection unit pb pb hsb hs b nwe1 nwe3 pba pbb npcs0 local bus interface audio bitstream dac pdc data[1..0] datan[1..0]
6 32058fs?avr32?08/08 at32uc3a 4.1 processor and architecture 4.1.1 avr32 uc cpu ? 32-bit load/store avr32a risc architecture. ? 15 general-purpose 32-bit registers. ? 32-bit stack pointer, program counter and link register reside in register file. ? fully orthogonal instruction set. ? privileged and unprivileged modes enabling efficient and secure operating systems. ? innovative instruction set together with variable instruction length ensu ring industry leading code density. ? dsp extention with saturating arithmetic, and a wide variet y of multiply instructions. ? 3 stage pipeline allows one instruction per clock cycle for most instructions. ? byte, half-word, word and double word memory access. ? multiple interrupt priority levels. ? mpu allows for operating s ystems with memory protection. 4.1.2 debug and test system ? ieee1149.1 compliant jtag and boundary scan ? direct memory access and programming capabilities through jtag interface ? extensive on-chip debug features in compliance with ieee-isto 5001-2003 (nexus 2.0) class 2+ ? low-cost nanotrace supported. ? auxiliary port for high-speed trace information ? hardware support for 6 program and 2 data breakpoints ? unlimited number of softw are breakpoints supported ? advanced program, data, ownership, and watchpoint trace supported 4.1.3 peripheral dma controller ? transfers from/to peripheral to/from any memory space without interven tion of the processor. ? next pointer support, forbids strong real -time constraints on buffer management. ? fifteen channels ? two for each usart ? two for each serial synchronous controller ? two for each serial peripheral interface ? one for each adc ? two for each twi interface 4.1.4 bus system ? high speed bus (hsb) matrix with 6 masters and 6 slaves handled ? handles requests from the cpu data fetch, cpu instruction fetch, pdca, usbb, ethernet controller, cpu sab, and to inte rnal flash, internal sram, peri pheral bus a, peripheral bus b, ebi. ? round-robin arbitration (three modes supported: no default master, last accessed default master, fixed default master) ? burst breaking with slot cycle limit ? one address decoder provided per master
7 32058fs?avr32?08/08 at32uc3a ? peripheral bus a able to run on at divided bus speeds compared to the high speed bus figure 4-1 gives an overview of the bus system. all modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the power manager. the figure identifies the number of master and slave interfaces of each module connected to the high speed bus, and which dma controller is connected to which peripheral.
8 32058fs?avr32?08/08 at32uc3a 5. signals description the following table gives details on the signal name classified by peripheral the signals are multiplexed with gpio pins as described in ?peripheral multiplexing on i/o lines? on page 30 . table 5-1. signal description list signal name function type active level comments power vddpll power supply for pll power input 1.65v to 1.95 v vddcore core power supply power input 1.65v to 1.95 v vddio i/o power supply power input 3.0v to 3.6v vddana analog power supply power input 3.0v to 3.6v vddin voltage regulator input supply power input 3.0v to 3.6v vddout voltage regulator output power output 1.65v to 1.95 v gndana analog ground ground gnd ground ground clocks, oscillators, and pll?s xin0, xin1, xin32 crystal 0, 1, 32 input analog xout0, xout1, xout32 crystal 0, 1, 32 output analog jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input auxiliary port - aux mcko trace data output clock output mdo0 - mdo5 trace data output output
9 32058fs?avr32?08/08 at32uc3a mseo0 - mseo1 trace frame control output evti_n event in output low evto_n event out output low power manager - pm gclk0 - gclk3 generic clock pins output reset_n reset pin input low real time counter - rtc rtc_clock rtc clock output watchdog timer - wdt wdtext external watchdog pin output external interrup t controller - eic extint0 - extint7 external interrupt pins input kps0 - kps7 keypad scan pins output nmi_n non-maskable interrupt pin input low ethernet mac - macb col collision detect input crs carrier sense and data valid input mdc management data clock output mdio management data input/output i/o rxd0 - rxd3 receive data input rx_clk receive clock input rx_dv receive data valid input rx_er receive coding error input speed speed txd0 - txd3 transmit data output tx_clk transmit clock or reference clock output tx_en transmit enable output tx_er transmit coding error output table 5-1. signal description list signal name function type active level comments
10 32058fs?avr32?08/08 at32uc3a external bus interface - hebi addr0 - addr23 address bus output cas column signal output low data0 - data15 data bus i/o ncs0 - ncs3 chip select output low nrd read signal output low nwait external wait signal input low nwe0 write enable 0 output low nwe1 write enable 1 output low nwe3 write enable 3 output low ras row signal output low sda10 sdram address 10 line output sdck sdram clock output sdcke sdram clock enable output sdcs0 sdram chip select output low sdwe sdram write enable output low general purpose input/output 2 - gpioa, gpiob, gpioc p0 - p31 parallel i/o controller gpioa i/o p0 - p31 parallel i/o controller gpiob i/o p0 - p5 parallel i/o controller gpioc i/o p0 - p31 parallel i/o controller gpiox i/o serial peripheral in terface - spi0, spi1 miso master in slave out i/o mosi master out slave in i/o npcs0 - npcs3 spi peripheral chip select i/o low sck clock output synchronous serial controller - ssc rx_clock ssc receive clock i/o table 5-1. signal description list signal name function type active level comments
11 32058fs?avr32?08/08 at32uc3a rx_data ssc receive data input rx_frame_sync ssc receive frame sync i/o tx_clock ssc transmit clock i/o tx_data ssc transmit data output tx_frame_sync ssc transmit frame sync i/o timer/counter - timer a0 channel 0 line a i/o a1 channel 1 line a i/o a2 channel 2 line a i/o b0 channel 0 line b i/o b1 channel 1 line b i/o b2 channel 2 line b i/o clk0 channel 0 external clock input input clk1 channel 1 external clock input input clk2 channel 2 external clock input input two-wire interface - twi scl serial clock i/o sda serial data i/o universal synchronous asynchronous receiver transmitter - usart0, usart1, usart2, usart3 clk clock i/o cts clear to send input dcd data carrier detect only usart1 dsr data set ready only usart1 dtr data terminal ready only usart1 ri ring indicator only usart1 rts request to send output rxd receive data input txd transmit data output table 5-1. signal description list signal name function type active level comments
12 32058fs?avr32?08/08 at32uc3a analog to digital converter - adc ad0 - ad7 analog input pins analog input advref analog positive reference voltage input analog input 2.6 to 3.6v pulse width modulator - pwm pwm0 - pwm6 pwm output pins output universal serial bus device - usb ddm usb device port data - analog ddp usb device port data + analog vbus usb vbus monitor and otg negociation analog input usbid id pin of the usb bus input usb_vbof usb vbus on/off: bu s power control port output audio bitstream dac (abdac) data0-data1 d/a data out outpu datan0-datan1 d/a data inverted out outpu table 5-1. signal description list signal name function type active level comments
13 32058fs?avr32?08/08 at32uc3a 6. package and pinout the device pins are multiplexed with peripheral functions as described in ?peripheral multiplexing on i/o lines? on page 30 . figure 6-1. tqfp100 pinout 125 26 50 51 75 76 100 table 6-1. tqfp100 package pinout 1 pb20 26 pa 0 5 51 pa 2 1 76 pb08 2 pb21 27 pa 0 6 52 pa 2 2 77 pb09 3 pb22 28 pa 0 7 53 pa 2 3 78 pb10 4 vddio 29 pa 0 8 54 pa 2 4 79 vddio 5 gnd 30 pa 0 9 55 pa 2 5 80 gnd 6 pb23 31 pa 1 0 56 pa 2 6 81 pb11 7 pb24 32 n/c 57 pa 2 7 82 pb12 8 pb25 33 pa 1 1 58 pa 2 8 83 pa 2 9 9 pb26 34 vddcore 59 vddana 84 pa 3 0 10 pb27 35 gnd 60 advref 85 pc02 11 vddout 36 pa 1 2 61 gndana 86 pc03 12 vddin 37 pa 1 3 62 vddpll 87 pb13 13 gnd 38 vddcore 63 pc00 88 pb14 14 pb28 39 pa 1 4 64 pc01 89 tms 15 pb29 40 pa 1 5 65 pb00 90 tck 16 pb30 41 pa 1 6 66 pb01 91 tdo 17 pb31 42 pa 1 7 67 vddio 92 tdi 18 reset_n 43 pa 1 8 68 vddio 93 pc04 19 pa 0 0 44 pa 1 9 69 gnd 94 pc05 20 pa 0 1 45 pa 2 0 70 pb02 95 pb15 21 gnd 46 vbus 71 pb03 96 pb16 22 vddcore 47 vddio 72 pb04 97 vddcore
14 32058fs?avr32?08/08 at32uc3a figure 6-2. lqfp144 pinout 23 pa 0 2 48 dm 73 pb05 98 pb17 24 pa 0 3 49 dp 74 pb06 99 pb18 25 pa 0 4 50 gnd 75 pb07 100 pb19 table 6-1. tqfp100 package pinout 136 37 72 73 108 109 144 table 6-2. vqfp144 package pinout 1 px00 37 gnd 73 pa 2 1 109 gnd 2 px01 38 px10 74 pa 2 2 110 px30 3 pb20 39 pa 0 5 75 pa 2 3 111 pb08 4 px02 40 px11 76 pa 2 4 112 px31 5 pb21 41 pa 0 6 77 pa 2 5 113 pb09 6 pb22 42 px12 78 pa 2 6 114 px32 7 vddio 43 pa 0 7 79 pa 2 7 115 pb10 8 gnd 44 px13 80 pa 2 8 116 vddio 9 pb23 45 pa 0 8 81 vddana 117 gnd 10 px03 46 px14 82 advref 118 px33 11 pb24 47 pa 0 9 83 gndana 119 pb11 12 px04 48 pa 1 0 84 vddpll 120 px34 13 pb25 49 n/c 85 pc00 121 pb12 14 pb26 50 pa 1 1 86 pc01 122 pa 2 9 15 pb27 51 vddcore 87 px20 123 pa 3 0 16 vddout 52 gnd 88 pb00 124 pc02 17 vddin 53 pa 1 2 89 px21 125 pc03 18 gnd 54 pa 1 3 90 pb01 126 pb13 19 pb28 55 vddcore 91 px22 127 pb14 20 pb29 56 pa 1 4 92 vddio 128 tms 21 pb30 57 pa 1 5 93 vddio 129 tck
15 32058fs?avr32?08/08 at32uc3a 22 pb31 58 pa 1 6 94 gnd 130 tdo 23 reset_n 59 px15 95 px23 131 tdi 24 px05 60 pa 1 7 96 pb02 132 pc04 25 pa 0 0 61 px16 97 px24 133 pc05 26 px06 62 pa 1 8 98 pb03 134 pb15 27 pa 0 1 63 px17 99 px25 135 px35 28 gnd 64 pa 1 9 100 pb04 136 pb16 29 vddcore 65 px18 101 px26 137 px36 30 pa 0 2 66 pa 2 0 102 pb05 138 vddcore 31 px07 67 px19 103 px27 139 pb17 32 pa 0 3 68 vbus 104 pb06 140 px37 33 px08 69 vddio 105 px28 141 pb18 34 pa 0 4 70 dm 106 pb07 142 px38 35 px09 71 dp 107 px29 143 pb19 36 vddio 72 gnd 108 vddio 144 px39 table 6-2. vqfp144 package pinout
16 32058fs?avr32?08/08 at32uc3a 7. power considerations 7.1 power supplies the at32uc3a has several types of power supply pins: ? vddio: powers i/o lines. voltage is 3.3v nominal. ? vddana: powers the adc voltage is 3.3v nominal. ? vddin: input voltage for the voltage regulator. voltage is 3.3v nominal. ? vddcore: powers the core, me mories, and peripherals. voltage is 1.8v nominal. ? vddpll: powers the pll. voltage is 1.8v nominal. the ground pins gnd are common to vddcore, vddio, vddpll. the ground pin for vddana is gndana. refer to ?power consumption? on page 42 for power consumption on the various supply pins. 3.3v vddana vddio vddin vddcore vddout vddpll advref 3.3v 1.8v vddana vddio vddin vddcore vddout vddpll advref single power supply dual power supply 1.8v regulator 1.8v regulator
17 32058fs?avr32?08/08 at32uc3a 7.2 voltage regulator 7.2.1 single power supply the at32uc3a embeds a voltage regulator that converts from 3.3v to 1.8v. the regulator takes its input voltage from vddin, and supplies the output voltage on vddo ut. vddout should be externally connected to the 1.8v domains. adequate input supply decouplin g is mandatory for vddin in or der to improve startup stability and reduce source voltage drop. two input decoup ling capacitors must be placed close to the chip. adequate output supply decoupling is mandator y for vddout to reduce ripple and avoid oscil- lations. the best way to achieve this is to use two capacitors in parallel between vddout and gnd as close to the chip as possible refer to section 12.3 on page 41 for decoupling capacitors values and regulator characteristics 7.2.2 dual power supply in case of dual power supply, vddin and vddout should be connected to ground to prevent from leakage current. 3.3v 1.8v vddin vddout 1.8v regulator c in1 c out1 c out2 c in2 vddin vddout
18 32058fs?avr32?08/08 at32uc3a 7.3 analog-to-digital conv erter (a.d.c) reference. the adc reference (advref) must be provi ded from an external source. two decoupling capacitors must be used to insure proper decoupling. refer to section 12.4 on page 41 for decoupling capacitors values and electrical characteristics. in case adc is not used, the advref pin s hould be connected to gnd to avoid extra consumption. advref c c vref1 vref2 3.3v
19 32058fs?avr32?08/08 at32uc3a 8. i/o line considerations 8.1 jtag pins tms, tdi and tck have pull-up resistors. tdo is an output, driven at up to vddio, and has no pull-up resistor. 8.2 reset_n pin the reset_n pin is a schmitt input and integrates a permanent pull-up resistor to vddio. as the product integrat es a power-on reset cell, the reset_n pin can be left unconnected in case no reset from the system needs to be applied to the product. 8.3 twi pins when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. when used as gpio-pins or used for other peripherals, the pins have the same characteristics as pio pins. 8.4 gpio pins all the i/o lines integrate a programmable pull-up resistor . programming of this pull-up resistor is performed independently for each i/o line through the gpio controllers. after reset, i/o lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column ?reset state? of the gpio controller multiplexing tables.
20 32058fs?avr32?08/08 at32uc3a 9. memories 9.1 embedded memories ? internal high-speed flash ? 512 kbytes (at32uc3a0512, at32uc3a1512) ? 256 kbytes (at32uc3a0256, at32uc3a1256) ? 128 kbytes (at32uc3a1128, at32uc3a2128) - 0 wait state access at up to 33 mhz in worst case conditions - 1 wait state access at up to 66 mhz in worst case conditions - pipelined flash architecture, allowing burst re ads from sequential fl ash locations, hiding penalty of 1 wait state access - pipelined flash architecture typically reduce s the cycle penalty of 1 wait state operation to only 15% compared to 0 wait state operation - 100 000 write cycles, 15-year data retention capability - 4 ms page programming time, 8 ms chip erase time - sector lock capabilities, boot loader protection, security bit - 32 fuses, erased during chip erase - user page for data to be preserved during chip erase ? internal high-speed sram, singl e-cycle access at full speed ? 64 kbytes (at32uc3a0512, at32uc3a0256, at32uc3a1512, at32uc3a1256) ? 32kbytes (at32uc3a1128) 9.2 physical memory map the system bus is implemented as a bus matrix . all system bus addresses are fixed, and they are never remapped in any way, not even in boot. note that avr32 uc cpu uses unsegmented translation, as described in the avr32 architecture manual. the 32-bit physical address space is mapped as follows: table 9-1. at32uc3a physical memory map device start address size at32uc3a0512 at32uc3a1512 at32uc3a0256 at32uc3a1256 at32uc3a0128 at32uc3a1128 embedded sram 0x0000_0000 64 kbyte 64 kbyte 64 kbyte 64 kbyte 32 kbyte 32 kbyte embedded flash 0x8000_0000 512 kbyte 512 kbyte 256 kbyte 256 kbyte 128 kbyte 128 kbyte ebi sram cs0 0xc000_0000 16 mbyte - 16 mbyte - 16 mbyte - ebi sram cs2 0xc800_0000 16 mbyte - 16 mbyte - 16 mbyte - ebi sram cs3 0xcc00_0000 16 mbyte - 16 mbyte - 16 mbyte - ebi sram cs1 /sdram cs0 0xd000_0000 128 mbyte - 128 mbyte - 128 mbyte - usb configuration 0xe000_0000 64 kbyte 64 kbyte 64 kb yte 64 kbyte 64 kbyte 64 kbyte hsb-pb bridge a 0xfffe_0000 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte hsb-pb bridge b 0xffff_0000 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte
21 32058fs?avr32?08/08 at32uc3a 9.3 bus matrix connections accesses to unused areas returns an error result to the master requesting such an access. the bus matrix has the several masters and slaves. each master has its own bus and its own decoder, thus allowing a different memory mapping per master. the master number in the table below can be used to index the hmatrix contro l registers. for example, mcfg0 is associated with the cpu data master interface. each slave has its own arbiter, thus allowing a different arbitration per slave. the slave number in the table below can be used to index the hmatrix control registers. for example, scfg3 is associated with the internal sram slave interface. table 9-2. flash memory parameters part number flash size ( flash_pw ) number of pages ( flash_p ) page size ( flash_w ) general purpose fuse bits ( flash_f ) at32uc3a0512 512 kbytes 1024 128 words 32 fuses at32uc3a1512 512 kbytes 1024 128 words 32 fuses at32uc3a0256 256 kbytes 512 128 words 32 fuses at32uc3a1256 256 kbytes 512 128 words 32 fuses at32uc3a1128 128 kbytes 64 128 words 32 fuses at32uc3a0128 128 kbytes 64 128 words 32 fuses table 9-3. high speed bus masters master 0 cpu data master 1 cpu instruction master 2 cpu sab master 3 pdca master 4 macb dma master 5 usbb dma table 9-4. high speed bus slaves slave 0 internal flash slave 1 hsb-pb bridge 0 slave 2 hsb-pb bridge 1 slave 3 internal sram slave 4 usbb dpram slave 5 ebi
22 32058fs?avr32?08/08 at32uc3a figure 9-1. hmatrix master / slave connections cpu data 0 cpu instruction 1 cpu sab 2 pdca 3 macb 4 internal flash 0 hsb-pb bridge 0 1 hsb-pb bridge 1 2 internal sram slave 3 usbb slave 4 ebi 5 usbb dma 5 hmatrix masters hmatrix slaves
23 32058fs?avr32?08/08 at32uc3a 10. peripherals 10.1 peripheral address map table 10-1. peripheral address mapping address peripheral name bus 0xe0000000 usbb usbb slave interface - usbb hsb 0xfffe0000 usbb usbb configuration interface - usbb pbb 0xfffe1000 hmatrix hmatrix configuration interface - hmatrix pbb 0xfffe1400 flashc flash controller - flashc pbb 0xfffe1800 macb macb configuration interface - macb pbb 0xfffe1c00 smc static memory controller configuration interface - smc pbb 0xfffe2000 sdramc sdram controller configuration interface - sdramc pbb 0xffff0000 pdca peripheral dma interface - pdca pba 0xffff0800 intc interrupt controller interface - intc pba 0xffff0c00 pm power manager - pm pba 0xffff0d00 rtc real time clock - rtc pba 0xffff0d30 wdt watchdog timer - wdt pba 0xffff0d80 eic external interrupt controller - eic pba 0xffff1000 gpio general purpose io controller - gpio pba 0xffff1400 usart0 universal synchronous asynchronous receiver transmitter - usart0 pba 0xffff1800 usart1 universal synchronous asynchronous receiver transmitter - usart1 pba
24 32058fs?avr32?08/08 at32uc3a 10.2 cpu local bus mapping some of the registers in the gpio module are mapped onto the cpu local bus, in addition to being mapped on the peripheral bus. these registers can therefore be reached both by accesses on the peripheral bus, and by accesses on the local bus. mapping these registers on the local bus allows cycle-deterministic toggling of gpio pins since the cpu and gpio are the only modules connected to this bus. also, since the local bus runs at cpu speed, one write or read operation can be pe rformed per clock cycle to the local bus- mapped gpio registers. 0xffff1c00 usart2 universal synchronous asynchronous receiver transmitter - usart2 pba 0xffff2000 usart3 universal synchronous asynchronous receiver transmitter - usart3 pba 0xffff2400 spi0 serial peripheral interface - spi0 pba 0xffff2800 spi1 serial peripheral interface - spi1 pba 0xffff2c00 twi two wire interface - twi pba 0xffff3000 pwm pulse width modulation controller - pwm pba 0xffff3400 ssc synchronous serial controller - ssc pba 0xffff3800 tc timer/counter - tc pba 0xffff3c00 adc analog to digital converter - adc pba table 10-1. peripheral address mapping (continued) address peripheral name bus
25 32058fs?avr32?08/08 at32uc3a the following gpio registers are mapped on the local bus: table 10-2. local bus mapped gpio registers port register mode local bus address access 0 output driver enable register (oder) write 0x4000_0040 write-only set 0x4000_0044 write-only clear 0x4000_0048 write-only toggle 0x4000_004c write-only output value register (ovr) write 0x4000_0050 write-only set 0x4000_0054 write-only clear 0x4000_0058 write-only toggle 0x4000_005c write-only pin value register (pvr) - 0x4000_0060 read-only 1 output driver enable register (oder) write 0x4000_0140 write-only set 0x4000_0144 write-only clear 0x4000_0148 write-only toggle 0x4000_014c write-only output value register (ovr) write 0x4000_0150 write-only set 0x4000_0154 write-only clear 0x4000_0158 write-only toggle 0x4000_015c write-only pin value register (pvr) - 0x4000_0160 read-only 2 output driver enable register (oder) write 0x4000_0240 write-only set 0x4000_0244 write-only clear 0x4000_0248 write-only toggle 0x4000_024c write-only output value register (ovr) write 0x4000_0250 write-only set 0x4000_0254 write-only clear 0x4000_0258 write-only toggle 0x4000_025c write-only pin value register (pvr) - 0x4000_0260 read-only
26 32058fs?avr32?08/08 at32uc3a 10.3 interrupt r equest signal map the various modules may output interrupt request signals. these signals are routed to the inter- rupt controller (intc), described in a later c hapter. the interrupt controller supports up to 64 groups of interrupt requests. each group can have up to 32 interrupt request signals. all interrupt signals in the same group share the same autov ector address and priority level. refer to the documentation for the individual submodules for a description of the semantics of the different interrupt requests. the interrupt request signals are co nnected to the intc as follows. 3 output driver enable register (oder) write 0x4000_0340 write-only set 0x4000_0344 write-only clear 0x4000_0348 write-only toggle 0x4000_034c write-only output value register (ovr) write 0x4000_0350 write-only set 0x4000_0354 write-only clear 0x4000_0358 write-only toggle 0x4000_035c write-only pin value register (pvr) - 0x4000_0360 read-only table 10-2. local bus mapped gpio registers port register mode local bus address access table 10-3. interrupt request signal map group line module signal 00 avr32 uc cpu with optional mpu and optional ocd sysblock compare 1 0 external interrupt controller eic 0 1 external interrupt controller eic 1 2 external interrupt controller eic 2 3 external interrupt controller eic 3 4 external interrupt controller eic 4 5 external interrupt controller eic 5 6 external interrupt controller eic 6 7 external interrupt controller eic 7 8 real time counter rtc 9 power manager pm 10 frequency meter freqm
27 32058fs?avr32?08/08 at32uc3a 2 0 general purpose input/output gpio 0 1 general purpose input/output gpio 1 2 general purpose input/output gpio 2 3 general purpose input/output gpio 3 4 general purpose input/output gpio 4 5 general purpose input/output gpio 5 6 general purpose input/output gpio 6 7 general purpose input/output gpio 7 8 general purpose input/output gpio 8 9 general purpose input/output gpio 9 10 general purpose input/output gpio 10 11 general purpose input/output gpio 11 12 general purpose input/output gpio 12 13 general purpose input/output gpio 13 3 0 peripheral dma controller pdca 0 1 peripheral dma controller pdca 1 2 peripheral dma controller pdca 2 3 peripheral dma controller pdca 3 4 peripheral dma controller pdca 4 5 peripheral dma controller pdca 5 6 peripheral dma controller pdca 6 7 peripheral dma controller pdca 7 8 peripheral dma controller pdca 8 9 peripheral dma controller pdca 9 10 peripheral dma controller pdca 10 11 peripheral dma controller pdca 11 12 peripheral dma controller pdca 12 13 peripheral dma controller pdca 13 14 peripheral dma controller pdca 14 4 0 flash controller flashc 50 universal synchronous/asynchronous receiver/transmitter usart0 60 universal synchronous/asynchronous receiver/transmitter usart1 70 universal synchronous/asynchronous receiver/transmitter usart2 80 universal synchronous/asynchronous receiver/transmitter usart3 table 10-3. interrupt request signal map
28 32058fs?avr32?08/08 at32uc3a 10.4 clock connections 10.4.1 timer/counters each timer/counter channel can independently select an internal or external clock source for its counter: 10.4.2 usarts each usart can be connected to an internally divided clock: 9 0 serial peripheral interface spi0 10 0 serial peripheral interface spi1 11 0 two-wire interface twi 12 0 pulse width modulation controller pwm 13 0 synchronous serial controller ssc 14 0 timer/counter tc0 1 timer/counter tc1 2 timer/counter tc2 15 0 analog to digital converter adc 16 0 ethernet mac macb 17 0 usb 2.0 otg interface usbb 18 0 sdram controller sdramc 19 0 audio bitstream dac dac table 10-3. interrupt request signal map table 10-4. timer/counter clock connections source name connection internal timer_clock1 32 khz oscillator timer_clock2 pba clock / 2 timer_clock3 pba clock / 8 timer_clock4 pba clock / 32 timer_clock5 pba clock / 128 external xc0 see section 10.7 xc1 xc2 table 10-5. usart clock connections usart source name connection 0 internal clk_div pba clock / 8 1 2 3
29 32058fs?avr32?08/08 at32uc3a 10.4.3 spis each spi can be connected to an internally divided clock: 10.5 nexus ocd aux port connections if the ocd trace system is enabled, the trace system will take control over a number of pins, irre- spectively of the pio configuration. two different ocd trace pi n mappings are possible, depending on the configuratio n of the ocd axs register. for details, see the avr32 uc tech- nical reference manual . 10.6 pdc handshake signals the pdc and the peripheral modules communicate through a set of handshake signals. the fol- lowing table defines the valid settings for the peripheral identifier (pid) in the pdc peripheral select register (psr). table 10-6. spi clock connections spi source name connection 0 internal clk_div pba clock or pba clock / 32 1 table 10-7. nexus ocd aux port connections pin axs=0 axs=1 evti_n pb19 pa08 mdo[5] pb16 pa27 mdo[4] pb14 pa26 mdo[3] pb13 pa25 mdo[2] pb12 pa24 mdo[1] pb11 pa23 mdo[0] pb10 pa22 evto_n pb20 pb20 mcko pb21 pa21 mseo[1] pb04 pa07 mseo[0] pb17 pa28 table 10-8. pdc handshake signals pid value peripheral module & direction 0adc 1 ssc - rx 2 usart0 - rx 3 usart1 - rx
30 32058fs?avr32?08/08 at32uc3a 10.7 peripheral multiplexing on i/o lines each gpio line can be assigned to one of 3 peripheral functions; a, b or c. the following table define how the i/o lines on the peripherals a, b and c are multiplexed by the gpio. 4 usart2 - rx 5 usart3 - rx 6twi - rx 7 spi0 - rx 8 spi1 - rx 9 ssc - tx 10 usart0 - tx 11 usart1 - tx 12 usart2 - tx 13 usart3 - tx 14 twi - tx 15 spi0 - tx 16 spi1 - tx 17 abdac table 10-8. pdc handshake signals pid value peripheral module & direction table 10-9. gpio controller func tion multiplexing tqfp100 vqfp144 pin gpio pin function a function b function c 19 25 pa00 gpio 0 usart0 - rxd tc - clk0 20 27 pa01 gpio 1 usart0 - txd tc - clk1 23 30 pa02 gpio 2 usart0 - clk tc - clk2 24 32 pa03 gpio 3 usart0 - rts eim - extint[4] dac - data[0] 25 34 pa04 gpio 4 usart0 - cts eim - extint[5] dac - datan[0] 26 39 pa05 gpio 5 usart1 - rxd pwm - pwm[4] 27 41 pa06 gpio 6 usart1 - txd pwm - pwm[5] 28 43 pa07 gpio 7 usart1 - clk pm - gclk[0] spi0 - npcs[3] 29 45 pa08 gpio 8 usart1 - rts spi0 - npcs[1] eim - extint[7] 30 47 pa09 gpio 9 usart1 - cts spi0 - npcs[2] macb - wol 31 48 pa10 gpio 10 spi0 - npcs[0] eim - extint[6] 33 50 pa11 gpio 11 spi0 - miso usb - usb_id 36 53 pa12 gpio 12 spi0 - mosi usb - usb_vbof 37 54 pa13 gpio 13 spi0 - sck 39 56 pa14 gpio 14 ssc - tx_frame_sync spi1 - npcs[0] ebi - ncs[0] 40 57 pa15 gpio 15 ssc - tx_clock spi1 - sck ebi - addr[20]
31 32058fs?avr32?08/08 at32uc3a 41 58 pa16 gpio 16 ssc - tx_data spi1 - mosi ebi - addr[21] 42 60 pa17 gpio 17 ssc - rx_data spi1 - miso ebi - addr[22] 43 62 pa18 gpio 18 ssc - rx_clock spi1 - npcs[1] macb - wol 44 64 pa19 gpio 19 ssc - rx_frame_sync spi1 - npcs[2] 45 66 pa20 gpio 20 eim - extint[8] spi1 - npcs[3] 51 73 pa21 gpio 21 adc - ad[0] eim - extint[0] usb - usb_id 52 74 pa22 gpio 22 adc - ad[1] eim - extint[1] usb - usb_vbof 53 75 pa23 gpio 23 adc - ad[2] eim - extint[2] dac - data[1] 54 76 pa24 gpio 24 adc - ad[3] eim - extint[3] dac - datan[1] 55 77 pa25 gpio 25 adc - ad[4] eim - scan[0] ebi - ncs[0] 56 78 pa26 gpio 26 adc - ad[5] eim - scan[1] ebi - addr[20] 57 79 pa27 gpio 27 adc - ad[6] eim - scan[2] ebi - addr[21] 58 80 pa28 gpio 28 adc - ad[7] eim - scan[3] ebi - addr[22] 83 122 pa29 gpio 29 twi - sda usart2 - rts 84 123 pa30 gpio 30 twi - scl usart2 - cts 65 88 pb00 gpio 32 macb - tx_clk usart2 - rts usart3 - rts 66 90 pb01 gpio 33 macb - tx_en usart2 - cts usart3 - cts 70 96 pb02 gpio 34 macb - txd[0] dac - data[0] 71 98 pb03 gpio 35 macb - txd[1] dac - datan[0] 72 100 pb04 gpio 36 macb - crs usart3 - clk ebi - ncs[3] 73 102 pb05 gpio 37 macb - rxd[0] dac - data[1] 74 104 pb06 gpio 38 macb - rxd[1] dac - datan[1] 75 106 pb07 gpio 39 macb - rx_er 76 111 pb08 gpio 40 macb - mdc 77 113 pb09 gpio 41 macb - mdio 78 115 pb10 gpio 42 macb - txd[2] usart3 - rxd ebi - sdck 81 119 pb11 gpio 43 macb - txd[3] usart3 - txd ebi - sdcke 82 121 pb12 gpio 44 macb - tx_er tc - clk0 ebi - ras 87 126 pb13 gpio 45 macb - rxd[2] tc - clk1 ebi - cas 88 127 pb14 gpio 46 macb - rxd[3] tc - clk2 ebi - sdwe 95 134 pb15 gpio 47 macb - rx_dv 96 136 pb16 gpio 48 macb - col usb - usb_id ebi - sda10 98 139 pb17 gpio 49 macb - rx_clk usb - usb_vbof ebi - addr[23] 99 141 pb18 gpio 50 macb - speed adc - trigger pwm - pwm[6] 100 143 pb19 gpio 51 pwm - pwm[0] pm - gclk[0] eim - scan[4] 1 3 pb20 gpio 52 pwm - pwm[1] pm - gclk[1] eim - scan[5] 2 5 pb21 gpio 53 pwm - pwm[2] pm - gclk[2] eim - scan[6] 3 6 pb22 gpio 54 pwm - pwm[3] pm - gclk[3] eim - scan[7] 6 9 pb23 gpio 55 tc - a0 usart1 - dcd table 10-9. gpio controller func tion multiplexing
32 32058fs?avr32?08/08 at32uc3a 7 11 pb24 gpio 56 tc - b0 usart1 - dsr 8 13 pb25 gpio 57 tc - a1 usart1 - dtr 9 14 pb26 gpio 58 tc - b1 usart1 - ri 10 15 pb27 gpio 59 tc - a2 pwm - pwm[4] 14 19 pb28 gpio 60 tc - b2 pwm - pwm[5] 15 20 pb29 gpio 61 usart2 - rxd pm - gclk[1] ebi - ncs[2] 16 21 pb30 gpio 62 usart2 - txd pm - gclk[2] ebi - sdcs 17 22 pb31 gpio 63 usart2 - clk pm - gclk[3] ebi - nwait 63 85 pc00 gpio 64 64 86 pc01 gpio 65 85 124 pc02 gpio 66 86 125 pc03 gpio 67 93 132 pc04 gpio 68 94 133 pc05 gpio 69 1 px00 gpio 100 ebi - data[10] usart0 - rxd 2 px01 gpio 99 ebi - data[9] usart0 - txd 4 px02 gpio 98 ebi - data[8] usart0 - cts 10 px03 gpio 97 ebi - data[7] usart0 - rts 12 px04 gpio 96 ebi - data[6] usart1 - rxd 24 px05 gpio 95 ebi - data[5] usart1 - txd 26 px06 gpio 94 ebi - data[4] usart1 - cts 31 px07 gpio 93 ebi - data[3] usart1 - rts 33 px08 gpio 92 ebi - data[2] usart3 - rxd 35 px09 gpio 91 ebi - data[1] usart3 - txd 38 px10 gpio 90 ebi - data[0] usart2 - rxd 40 px11 gpio 109 ebi - nwe1 usart2 - txd 42 px12 gpio 108 ebi - nwe0 usart2 - cts 44 px13 gpio 107 ebi - nrd usart2 - rts 46 px14 gpio 106 ebi - ncs[1] tc - a0 59 px15 gpio 89 ebi - addr[19] usart3 - rts tc - b0 61 px16 gpio 88 ebi - addr[18] usart3 - cts tc - a1 63 px17 gpio 87 ebi - addr[17] tc - b1 65 px18 gpio 86 ebi - addr[16] tc - a2 67 px19 gpio 85 ebi - addr[15] eim - scan[0] tc - b2 87 px20 gpio 84 ebi - addr[14] eim - scan[1] tc - clk0 89 px21 gpio 83 ebi - addr[13] eim - scan[2] tc - clk1 91 px22 gpio 82 ebi - addr[12] eim - scan[3] tc - clk2 95 px23 gpio 81 ebi - addr[11] eim - scan[4] 97 px24 gpio 80 ebi - addr[10] eim - scan[5] table 10-9. gpio controller func tion multiplexing
33 32058fs?avr32?08/08 at32uc3a 10.8 oscillator pinout the oscillators are not ma pped to the normal a,b or c functi ons and their muxings are controlled by registers in the power manager (pm). please refer to the power manager chapter for more information about this. 10.9 usart configuration 99 px25 gpio 79 ebi - addr[9] eim - scan[6] 101 px26 gpio 78 ebi - addr[8] eim - scan[7] 103 px27 gpio 77 ebi - addr[7] spi0 - miso 105 px28 gpio 76 ebi - addr[6] spi0 - mosi 107 px29 gpio 75 ebi - addr[5] spi0 - sck 110 px30 gpio 74 ebi - addr[4] spi0 - npcs[0] 112 px31 gpio 73 ebi - addr[3] spi0 - npcs[1] 114 px32 gpio 72 ebi - addr[2] spi0 - npcs[2] 118 px33 gpio 71 ebi - addr[1] spi0 - npcs[3] 120 px34 gpio 70 ebi - addr[0] spi1 - miso 135 px35 gpio 105 ebi - data[15] spi1 - mosi 137 px36 gpio 104 ebi - data[14] spi1 - sck 140 px37 gpio 103 ebi - data[13] spi1 - npcs[0] 142 px38 gpio 102 ebi - data[12] spi1 - npcs[1] 144 px39 gpio 101 ebi - data[11] spi1 - npcs[2] table 10-9. gpio controller func tion multiplexing table 10-10. oscillator pinout tqfp100 pin vqfp144 pin pad oscillator pin 85 124 pc02 xin0 93 132 pc04 xin1 63 85 pc00 xin32 86 125 pc03 xout0 94 133 pc05 xout1 64 86 pc01 xout32 table 10-11. usart supported mode spi rs485 iso7816 irda modem manchester encoding usart0yesnonononono u s a r t 1 ye s ye s ye s ye s ye s ye s usart2yesnonononono usart3yesnonononono
34 32058fs?avr32?08/08 at32uc3a 10.10 gpio the gpio open drain feature (gpio odmer regi ster (open drain mode enable register)) is not available for this device. 10.11 peripheral overview 10.11.1 external bus interface ? optimized for application memory space support ? integrates two external memory controllers: ? static memory controller ? sdram controller ? optimized external bus: ?16-bit data bus ? 24-bit address bus, up to 16-mbytes addressable ? optimized pin multiplexing to redu ce latencies on external memories ? 4 sram chip selects, 1sdram chip select: ? static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs2 ? static memory controller on ncs3 10.11.2 static memory controller ? 4 chip selects available ? 64-mbyte address space per chip select ? 8-, 16-bit data bus ? word, halfword, byte transfers ? byte write or by te select lines ? programmable setup, pulse and hold ti me for read signals per chip select ? programmable setup, pulse and hold time for write signals per chip select ? programmable data float time per chip select ? compliant with lcd module ? external wait request ? automatic switch to slow clock mode ? asynchronous read in page mode supporte d: page size ranges from 4 to 32 bytes 10.11.3 sdram controller ? numerous configurations supported ? 2k, 4k, 8k row address memory parts ? sdram with two or four internal banks ? sdram with 16-bit data path ? programming facilities ? word, half-word, byte access ? automatic page break when memory boundary has been reached ? multibank ping-pong access ? timing parameters specified by software ? automatic refresh operation, refresh rate is programmable ? energy-saving capabilities ? self-refresh, power-down and deep power modes supported
35 32058fs?avr32?08/08 at32uc3a ? supports mobile sdram devices ? error detection ? refresh error interrupt ? sdram power-up initialization by software ? cas latency of 1, 2, 3 supported ? auto precharge command not used 10.11.4 usb controller ? usb 2.0 compliant, full-/low-speed (f s/ls) and on-the-go (otg), 12 mbit/s ? 7 pipes/endpoints ? 960 bytes of embedded dual-port ram (dpram) for pipes/endpoints ? up to 2 memory banks per pipe/endpoint (not for control pipe/endpoint) ? flexible pipe/endpoint configuration and management with dedicated dma channels ? on-chip transceivers including pull-ups 10.11.5 serial peripheral interface ? supports communication with serial external devices ? four chip selects with extern al decoder support allow co mmunication with up to 15 peripherals ? serial memories, such as da taflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, l cd controllers, can controllers and sensors ? external co-processors ? master or slave serial peripheral bus interface ? 8- to 16-bit programmable da ta length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? very fast transfers supported ? transfers with baud rates up to peripheral bus a (pba) max frequency ? the chip select line may be left active to speed up transfer s on the same device 10.11.6 two-wire interface ? high speed up to 400kbit/s ? compatibility with standard two-wire serial memory ? one, two or three bytes for slave address ? sequential read/write operations 10.11.7 usart ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in a synchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by-16 over-sampling receiver frequency ? hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection
36 32058fs?avr32?08/08 at32uc3a ? optional manchester encoding ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? irda modulation and demodulation ? communication at up to 115.2 kbps ? test modes ? remote loopback, local loopback, automatic echo ? spi mode ? master or slave ? serial clock programmable phase and polarity ? spi serial clock (sck) frequency up to internal clock frequency pba/4 ? supports connection of two peripheral dma controller channels (pdc) ? offers buffer transfer without processor intervention 10.11.8 serial synchronous controller ? provides serial synchronous communication links used in audio and tel ecom applications (with codecs in master or slave modes, i2s, tdm buses, magnetic card reader, etc.) ? contains an independent receiver and transmitter and a common clock divider ? offers a configurable frame sync and data length ? receiver and transmitter can be programmed to st art automatically or on detection of different event on the frame sync signal ? receiver and transmitter include a data signal, a cloc k signal and a frame synchronization signal 10.11.9 timer counter ? three 16-bit timer counter channels ? wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ? delay timing ? pulse width modulation ? up/down capabilities ? each channel is user-conf igurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals ? two global registers that ac t on all three tc channels 10.11.10 pulse width modulation controller ? 7 channels, one 20-bit counter per channel ? common clock generator, providing thirteen different clocks ? a modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs ? independent channel programming ? independent enable disable commands ? independent clock ? independent period and duty cycle, with double bufferization ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform
37 32058fs?avr32?08/08 at32uc3a 10.11.11 ethernet 10/100 mac ? compatibility with ieee standard 802.3 ? 10 and 100 mbits per second data throughput capability ? full- and half-duplex operations ? mii or rmii interface to the physical layer ? register interface to address, da ta, status and control registers ? dma interface, operating as a ma ster on the memory controller ? interrupt generation to signal receive and transmit completion ? 28-byte transmit and 28-byte receive fifos ? automatic pad and crc genera tion on transmitted frames ? address checking logic to recognize four 48-bit addresses ? support promiscuous mode where all valid frames are copied to memory ? support physical layer management through mdio interface control of alarm and update time/calendar data 10.11.12 audio bitstream dac ? digital stereo dac ? oversampled d/a conversion architecture ? oversampling ratio fixed 128x ? fir equalization filter ? digital interpolation filter: comb4 ? 3rd order sigma-delta d/a converters ? digital bitstream outputs ? parallel interface ? connected to peripheral dma controller for background transfer wi thout cpu intervention
38 32058fs?avr32?08/08 at32uc3a 11. boot sequence this chapter summarizes the boot sequence of the at32uc3a. the behaviour after power-up is controlled by the power manager. for specific details, refer to section 13. ?power manager (pm)? on page 55 . 11.1 starting of clocks after power-up, the device will be held in a reset state by the power-on reset circuitry, until the power has stabilized throughout the device. once the power has stabilized, the device will use the internal rc oscilla tor as clock source. on system start-up, the plls are disabled. all clocks to all modules are running. no clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the internal rc oscillator. 11.2 fetching of initial instructions after reset has been released, the avr32 uc cpu starts fetching instructions from the reset address, which is 0x8000_0000. this address points to the first address in the internal flash. the code read from the internal flash is free to configure the system to use for example the plls, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals.
39 32058fs?avr32?08/08 at32uc3a 12. electrical characteristics 12.1 absolute maximum ratings* operating temperature......................................-40 ? c to +85 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .......................................................... ....- 60c to +150c voltage on input pin with respect to ground-o.3v to 5.5v maximum operating voltage (vddcore, vddpll) ..... 1.95v maximum operating voltage (vddio).............................. 3.6v total dc output current on all i/o pin for tqfp100 packag ................................................... 370 ma for lqgp144 package ................................................. 470 ma
40 32058fs?avr32?08/08 at32uc3a 12.2 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise spec- ified and are certified for a junction temperature up to t j = 100c. symbol parameter condition min. typ. max units v vddcor e dc supply core 1.65 1.95 v v vddpll dc supply pll 1.65 1.95 v v vddio dc supply peripheral i/os 3.0 3.6 v v ref analog reference voltage 2.6 3.6 v v il input low-level voltage -0.3 +0.8 v v ih input high-level voltage all gpios except for pc00, pc01, pc02, pc03, pc04, pc05. 2.0 5.5v v pc00, pc01, pc02, pc03, pc04, pc05. 2.0 3.6v v v ol output low-level voltage i ol =-4ma 0.4 v v oh output high-level voltage i ol =4ma v vddio - 0.4 v i leak input leakage current pullup resistors disabled 1 a c in input capacitance tqfp100 package 7 pf lqfp144 package 7 pf r pullup pull-up resistance 10k ohm i o output current 4ma i sc static current on v vddcore = 1.8v, cpu is in static mode t a =25c tbd a all inputs driven; reset_n=1, t a =85c tbd tbd a i scr static current of internal regulator low power mode (stop, deep stop or static t a =25c 10 a
41 32058fs?avr32?08/08 at32uc3a 12.3 regulator characteristics 12.3.1 electrical characteristics 12.3.2 decoupling requirements 12.4 analog characteristics 12.4.1 electrical characteristics 12.4.2 decoupling requirement s 12.4.3 bod table 12-1. bodlevel values the values in table 12-1 describes the values of the bodlevel in t he flash fgpfr register. symbol parameter condition min. typ. max. units v vddin supply voltage (input) 2.7 3.3 3.6 v v vddout supply voltage (output) 1.81 1.85 1.89 v i out maximum dc output current with v vddin = 3.3v 100 ma maximum dc output current with v vddin = 2.7v 90 ma symbol parameter condition typ. techno. units c in1 input regulator capacitor 1 1 npo nf c in2 input regulator capacitor 2 4.7 x7r uf c out1 output regulator capacitor 1 470 npo pf c out2 output regulator capacitor 2 2.2 x7r uf symbol parameter condition min. typ. max. units v advref analog voltage reference (input) 2.6 3.6 v symbol parameter condition typ. techno. units c vref1 voltage reference capacitor 1 10 - nf c vref2 voltage reference capacitor 2 1 - uf bodlevel value typ. units. 000000b 1.58 v 010111b 1.62 v 011111b 1.67 v 100111b 1.77 v 111111b 1.92 v
42 32058fs?avr32?08/08 at32uc3a 12.5 power consumption the values in table 12-2 and table 12-3 on page 43 are measured values of power consump- tion with operating conditions as follows: ?v ddio = 3.3v ?v ddcore = v ddpll = 1.8v ?t a = 25 c, t a = 85 c ?i/os are inactive figure 12-1. measurement setup internal voltage regulator amp0 amp1 vddana vddio vddin vddout vddcore vddpll
43 32058fs?avr32?08/08 at32uc3a these figures represent the power consum ption measured on the power supplies. table 12-2. power consumption for different modes (1) mode conditions consumption typ. unit active cpu running from flash. cpu clocked from pll0 at f mhz voltage regulator is on. xin0 : external clock. (1) xin1 stopped. xin32 stopped pll0 running all peripheral clocks activated. gpios on internal pull-up. jtag unconnected with ext pull-up. f = 12 mhz 9 ma f = 24 mhz 16 ma f = 36mhz 23 ma f = 50 mhz 31.5 ma f = 60 mhz 37 ma static typ : ta = 25 c cpu is in static mode gpios on internal pull-up. all peripheral clocks de-activated. dm and dp pins connected to ground. xin0,xin1 and xin2 are stopped on amp0 25 ua on amp1 14 ua 1. core frequency is generated from xin0 using the pll so that 140 mhz < fpll0 < 160 mhz and 10 mhz < fxin0 < 12mhz table 12-3. power consumption by peripheral in active mode peripheral consumption unit gpio 37 a/mhz smc 10 sdramc 4 adc 18 ebi 31 intc 25 twi 14 macb 45 pdca 30 pwm 36 rtc 7 spi 13 ssc 13 tc 10 usart 35 usb 45
44 32058fs?avr32?08/08 at32uc3a 12.6 clock characteristics these parameters are given in the following conditions: ?v ddcore = 1.8v ? ambient temperature = 25c 12.6.1 cpu/hsb clock characteristics 12.6.2 pba clock characteristics 12.6.3 pbb clock characteristics 12.6.4 xin clock characteristics 12.7 crystal oscillat or characteristis the following characteristics are applicabl e to the operating temperature range: t a = -40c to 85c and worst case of power supply, unless otherwise specified. table 12-4. core clock waveform parameters symbol parameter conditions min max units 1/(t cpcpu ) cpu clock frequency 66 mhz t cpcpu cpu clock period 15,15 ns table 12-5. pba clock waveform parameters symbol parameter conditions min max units 1/(t cppba ) pba clock frequency 66 mhz t cppba pba clock period 15,15 ns table 12-6. pbb clock waveform parameters symbol parameter conditions min max units 1/(t cppbb ) pbb clock frequency 66 mhz t cppbb pbb clock period 15,15 ns table 12-7. xin clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency external clock 50 mhz crystal 3 20 mhz t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin c in xin input capacitance tbd pf
45 32058fs?avr32?08/08 at32uc3a 12.7.1 32 khz oscillator characteristics note: 1. c l is the equivalent load capacitance. 12.7.2 main oscillators characteristics notes: 1. c s is the shunt capacitance 12.7.3 pll characteristics table 12-8. 32 khz oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32 768 hz duty cycle 40 50 60 % c l equivalent load capacitance 6 12.5 pf t st startup time c l = 6pf (1) c l = 12.5pf (1) 600 1200 ms i osc current consumption active mode 1.8 a standby mode 0.1 a table 12-9. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 0.45 16 mhz c l1 , c l2 internal load capacitance (c l1 = c l2 ) 12 pf c l equivalent load capacitance tbd pf duty cycle 40 50 60 % t st startup time tbd ms i osc current consumption active mode @tbd mhz tbd a standby mode @tbd v tbd a table 12-10. phase lock loop characteristics symbol parameter conditions min typ max unit f out output frequency 80 240 mhz f in input frequency tbd tbd mhz i pll current consumption active mode tbd ma standby mode tbd a
46 32058fs?avr32?08/08 at32uc3a 12.8 adc characteristics notes: 1. corresponds to 13 clock cycles at 5 mhz: 3 clock cycles for track and hold ac quisition time and 10 clock cycles for conversion. 2. corresponds to 15 clock cycles at 8 mh z: 5 clock cycles for track and hold acqu isition time and 10 clock cycles for conversion. table 12-11. channel conversion time and adc clock parameter conditions min typ max units adc clock frequency 10-bit resolution mode 5 mhz adc clock frequency 8-bit resolution mode 8 mhz startup time return from idle mode 20 s track and hold acquisition time 600 ns conversion time adc clock = 5 mhz 2 s conversion time adc clock = 8 mhz 1.25 s throughput rate adc clock = 5 mhz 384 (1) ksps throughput rate adc clock = 8 mhz 533 (2) ksps table 12-12. external voltage reference input parameter conditions min typ max units advref input voltage range 2.6 vddana v advref average current on 13 samples with adc clock = 5 mhz 200 250 a current consumption on vddana tbd ma table 12-13. analog inputs parameter min typ max units input voltage range 0v advref input leakage current tbd a input capacitance 17 pf table 12-14. transfer characteristics parameter conditions min typ max units resolution 10 bit absolute accura cy f=5mhz 0.8 lsb integral non-linearity f=5mhz 0.35 0.5 lsb differential non-linearity f=5mhz 0.3 0.5 lsb offset error f=5mhz -0.5 0.5 lsb gain error f=5mhz -0.5 0.5 lsb
47 32058fs?avr32?08/08 at32uc3a 12.9 ebi timings these timings are given for worst case process, t = 85 ? c, vddcore = 1.65v, vddio = 3v and 40 pf load capacitance. note: 1. the maximum frequency of the smc interface is the same as the max frequency for the hsb. note: 1. hold length = total cycle duration - setup duration - pulse duration. ?hold length? is for ?ncs rd hold length? or ?nrd hold length?. table 12-15. smc clock signal. symbol parameter max (1) units 1/(t cpsmc ) smc controller clock frequency 1/(t cpcpu )mhz table 12-16. smc read signals with hold settings symbol parameter min units nrd controlled (read_mode = 1) smc 1 data setup before nrd high 12 ns smc 2 data hold after nrd high 0 smc 3 nrd high to nbs0/a0 change (1) nrd hold length * t cpsmc - 1.3 smc 4 nrd high to nbs1 change (1) nrd hold length * t cpsmc - 1.3 smc 5 nrd high to nbs2/a1 change (1) nrd hold length * t cpsmc - 1.3 smc 6 nrd high to nbs3 change (1) nrd hold length * t cpsmc - 1.3 smc 7 nrd high to a2 - a25 change (1) nrd hold length * t cpsmc - 1.3 smc 8 nrd high to ncs inactive (1) (nrd hold length - ncs rd hold length) * t cpsmc - 2.3 smc 9 nrd pulse width nrd pulse length * t cpsmc - 1.4 nrd controlled (read_mode = 0) smc 10 data setup before ncs high 11.5 ns smc 11 data hold after ncs high 0 smc 12 ncs high to nbs0/a0 change (1) ncs rd hold length * t cpsmc - 2.3 smc 13 ncs high to nbs0/a0 change (1) ncs rd hold length * t cpsmc - 2.3 smc 14 ncs high to nbs2/a1 change (1) ncs rd hold length * t cpsmc - 2.3 smc 15 ncs high to nbs3 change (1) ncs rd hold length * t cpsmc - 2.3 smc 16 ncs high to a2 - a25 change (1) ncs rd hold length * t cpsmc - 4 smc 17 ncs high to nrd inactive (1) ncs rd hold length - nrd hold length)* t cpsmc - 1.3 smc 18 ncs pulse width ncs rd pulse length * t cpsmc - 3.6
48 32058fs?avr32?08/08 at32uc3a note: 1. hold length = total cycle duration - setup duration - pulse duration. ?hold length? is for ?ncs wr hold length? or ?nwe hold length" table 12-17. smc read signals with no hold settings symbol parameter min units nrd controlled (read_mode = 1) smc 19 data setup before nrd high 13.7 ns smc 20 data hold after nrd high 1 nrd controlled (read_mode = 0) smc 21 data setup before ncs high 13.3 ns smc 22 data hold after ncs high 0 table 12-18. smc write signals with hold settings symbol parameter min units nrd controlled (read_mode = 1) smc 23 data out valid before nwe high (nwe pulse length - 1) * t cpsmc - 0.9 ns smc 24 data out valid after nwe high (1) nwe hold length * t cpsmc - 6 smc 25 nwe high to nbs0/a0 change (1) nwe hold length * t cpsmc - 1.9 smc 26 nwe high to nbs1 change (1) nwe hold length * t cpsmc - 1.9 smc 29 nwe high to nbs2/a1 change (1) nwe hold length * t cpsmc - 1.9 smc 30 nwe high to nbs3 change (1) nwe hold length * t cpsmc - 1.9 smc 31 nwe high to a2 - a25 change (1) nwe hold length * t cpsmc - 1.7 smc 32 nwe high to ncs inactive (1) (nwe hold length - n cs wr hold length)* t cpsmc - 2.9 smc 33 nwe pulse width nwe pulse length * t cpsmc - 0.9 nrd controlled (read_mode = 0) smc 34 data out valid before ncs high (ncs wr pulse length - 1)* t cpsmc - 4.6 ns smc 35 data out valid after ncs high (1) ncs wr hold length * t cpsmc - 5.8 smc 36 ncs high to nwe inactive (1) (ncs wr hold length - nwe hold length)* t cpsmc - 0.6
49 32058fs?avr32?08/08 at32uc3a figure 12-2. smc signals for ncs controlled accesses. table 12-19. smc write signals with no hold settings (nwe controlled only). symbol parameter min units smc 37 nwe rising to a2-a25 valid 5.4 ns smc 38 nwe rising to nbs0/a0 valid 5 smc 39 nwe rising to nbs1 change 5 smc 40 nwe rising to a1/nbs2 change 5 smc 41 nwe rising to nbs3 change 5 smc 42 nwe rising to ncs rising 5.1 smc 43 data out valid before nwe risi ng (nwe pulse length - 1) * t cpsmc - 1.2 smc 44 data out valid after nwe rising 5 smc 45 nwe pulse width nwe pulse length * t cpsmc - 0.9 nrd nc s d0 - d15 nwe a2-a25 a0/a1/nb s [ 3 :0] s mc 3 4 s mc 3 5 s mc10 s mc11 s mc16 s mc15 s mc22 s mc21 s mc17 s mc1 8 s mc14 s mc1 3 s mc12 s mc1 8 s mc17 s mc16 s mc15 s mc14 s mc1 3 s mc12 s mc1 8 s mc 3 6 s mc16 s mc15 s mc14 s mc1 3 s mc12
50 32058fs?avr32?08/08 at32uc3a figure 12-3. smc signals for nrd and nrw controlled accesses. 12.9.1 sdram signals these timings are given for 10 pf load on sdck and 40 pf on other signals. note: 1. the maximum frequency of the sdramc interface is the same as the max frequency for the hsb. nrd ncs d0 - d15 nwe a2-a25 a0/a1/nbs[3:0] smc7 smc19 smc20 smc43 smc37 smc42 smc8 smc1 smc2 smc23 smc24 smc32 smc7 smc8 smc6 smc5 smc4 smc3 smc9 smc41 smc40 smc39 smc38 smc45 smc9 smc6 smc5 smc4 smc3 smc33 smc30 smc29 smc26 smc25 smc31 smc44 table 12-20. sdram clock signal. symbol parameter max (1) units 1/(t cpsdck ) sdram controller clock frequency 1/(t cpcpu )mhz table 12-21. sdram clock signal. symbol parameter min units sdramc 1 sdcke high before sdck rising edge 7.4 ns sdramc 2 sdcke low after sdck rising edge 3.2 sdramc 3 sdcke low before sdck rising edge 7 sdramc 4 sdcke high after sdck rising edge 2.9 sdramc 5 sdcs low before sdck rising edge 7.5 sdramc 6 sdcs high after sdck rising edge 1.6 sdramc 7 ras low before sdck rising edge 7.2 sdramc 8 ras high after sdck rising edge 2.3 sdramc 9 sda10 change before sdck rising edge 7.6 sdramc 10 sda10 change after sdck rising edge 1.9
51 32058fs?avr32?08/08 at32uc3a sdramc 11 address change before sdck rising edge 6.2 ns sdramc 12 address change after sdck rising edge 2.2 sdramc 13 bank change before sdck rising edge 6.3 sdramc 14 bank change after sdck rising edge 2.4 sdramc 15 cas low before sdck rising edge 7.4 sdramc 16 cas high after sdck rising edge 1.9 sdramc 17 dqm change before sdck rising edge 6.4 sdramc 18 dqm change after sdck rising edge 2.2 sdramc 19 d0-d15 in setup before sdck rising edge 9 sdramc 20 d0-d15 in hold after sdck rising edge 0 sdramc 23 sdwe low before sdck rising edge 7.6 sdramc 24 sdwe high after sdck rising edge 1.8 sdramc 25 d0-d15 out valid before sdck rising edge 7.1 sdramc 26 d0-d15 out valid after sdck rising edge 1.5 table 12-21. sdram clock signal. symbol parameter min units
52 32058fs?avr32?08/08 at32uc3a figure 12-4. sdramc signals relative to sdck. ras a0 - a9, a11 - a13 d0 - d15 read sdck sda10 d0 - d15 to write sdramc 1 sdcke sdramc 2 sdramc 3 sdramc 4 sdcs sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 7 sdramc 8 cas sdramc 15 sdramc 16 sdramc 15 sdramc 16 sdwe sdramc 23 sdramc 24 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 11 sdramc 12 sdramc 11 sdramc 12 sdramc 11 sdramc 12 ba0/ba1 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 17 sdramc 18 sdramc 17 sdramc 18 dqm0 - dqm3 sdramc 19 sdramc 20 sdramc 25 sdramc 26
53 32058fs?avr32?08/08 at32uc3a 12.10 jtag timings 12.10.1 jtag interface signals note: 1. v vddio from 3.0v to 3.6v, maximum external capacitor = 40pf table 12-22. jtag interface timing specification symbol parameter conditions min max units jtag 0 tck low half-period (1) 6ns jtag 1 tck high half-period (1) 3ns jtag 2 tck period (1) 9ns jtag 3 tdi, tms setup before tck high (1) 1ns jtag 4 tdi, tms hold after tck high (1) 0ns jtag 5 tdo hold time (1) 4ns jtag 6 tck low to tdo valid (1) 6ns jtag 7 device inputs setup time (1) ns jtag 8 device inputs hold time (1) ns jtag 9 device outputs hold time (1) ns jtag 10 tck to device outputs valid (1) ns
54 32058fs?avr32?08/08 at32uc3a figure 12-5. jtag interface signals 12.11 spi characteristics figure 12-6. spi master mode with (cpol = ncpha = 0) or (cpol= ncpha= 1) tck jtag 9 tms/tdi tdo device outputs jtag 5 jtag 4 jtag 3 jtag 0 jtag 1 jtag 2 jtag 10 device inputs jtag 8 jtag 7 jtag 6 spck miso mosi spi 2 spi 0 spi 1
55 32058fs?avr32?08/08 at32uc3a figure 12-7. spi master mode with (cpol=0 and ncpha=1) or (cpol=1 and ncpha=0) figure 12-8. spi slave mode with (cpol=0 and ncpha=1) or (cpol=1 and ncpha=0) figure 12-9. spi slave mode with (cpol = ncph a = 0) or (cpol= ncpha= 1) spck miso mosi spi 5 spi 3 spi 4 spck miso mosi spi 6 spi 7 spi 8 spck miso mosi spi 9 spi 10 spi 11
56 32058fs?avr32?08/08 at32uc3a notes: 1. 3.3v domain: v vddio from 3.0v to 3.6v, maximum external capacitor = 40 pf. 2. t cpmck : master clock period in ns. 12.12 macb characteristics notes: 1. f: mck frequency (mhz) 2. v vddio from 3.0v to 3.6v, maximum external capacitor = 20 pf table 12-23. spi timings symbol parameter conditions min max units spi 0 miso setup time before spc k rises (master) 3.3v domain (1) 22 + (t cpmck )/2 (2) ns spi 1 miso hold time after spck rises (master) 3.3v domain (1) 0ns spi 2 spck rising to mosi de lay (master) 3.3v domain (1) 7ns spi 3 miso setup time before spc k falls (master) 3.3v domain (1) 22 + (t cpmck )/2 (2) ns spi 4 miso hold time after spck falls (master) 3.3v domain (1) 0ns spi 5 spck falling to mosi dela y (master) 3.3v domain (1) 7ns spi 6 spck falling to miso delay (slave) 3.3v domain (1) 26.5 ns spi 7 mosi setup time before spc k rises (slave) 3.3v domain (1) 0ns spi 8 mosi hold time after spck rises (slave) 3.3v domain (1) 1.5 ns spi 9 spck rising to miso delay (slave) 3.3v domain (1) 27 ns spi 10 mosi setup time before spc k falls (slave) 3.3v domain (1) 0ns spi 11 mosi hold time after spck falls (slave) 3.3v domain (1) 1ns table 12-24. ethernet mac signals symbol parameter conditi ons min (ns) max (ns) emac 1 setup for emdio from emdc rising load: 20pf (2) emac 2 hold for emdio from emdc rising load: 20pf (2) emac 3 emdio toggling from emdc falling load: 20pf (2) table 12-25. ethernet mac mii specific signals symbol parameter conditi ons min (ns) max (ns) emac 4 setup for ecol from etxck rising load: 20pf (1) 3 emac 5 hold for ecol from etxck rising load: 20pf (1) 0 emac 6 setup for ecrs from etxck rising load: 20pf (1) 3 emac 7 hold for ecrs from etxck rising load: 20pf (1) 0 emac 8 etxer toggling from etxck rising load: 20pf (1) 15 emac 9 etxen toggling from etxck rising load: 20pf (1) 15 emac 10 etx toggling from etxck rising load: 20pf (1) 15 emac 11 setup for erx from erxck load: 20pf (1) 1
57 32058fs?avr32?08/08 at32uc3a note: 1. v vddio from 3.0v to 3.6v, maximum external capacitor = 20 pf figure 12-10. ethernet mac mii mode emac 12 hold for erx from erxck load: 20pf (1) 1.5 emac 13 setup for erxer from erxck load: 20pf (1) 1 emac 14 hold for erxer from erxck load: 20pf (1) 0.5 emac 15 setup for erxdv from erxck load: 20pf (1) 1.5 emac 16 hold for erxdv from erxck load: 20pf (1) 1 table 12-25. ethernet mac mii specific signals symbol parameter conditi ons min (ns) max (ns) emdc emdio ecol ecrs etxck etxer etxen etx[3:0] erxck erx[3:0] erxer erxdv emac 3 emac 1 emac 2 emac 4 emac 5 emac 6 emac 7 emac 8 emac 9 emac 10 emac 11 emac 12 emac 13 emac 14 emac 15 emac 16
58 32058fs?avr32?08/08 at32uc3a figure 12-11. ethernet mac rmii mode 12.13 flash characteristics the following table gives the device maximum op erating frequency depending on the field fws of the flash fsr register. this field defines the number of wait states required to access the flash memory. table 12-26. ethernet mac rmii specific signals symbol parameter min (ns) max (ns) emac 21 etxen toggling from erefck rising 7 14.5 emac 22 etx toggling from erefck rising 7 14.7 emac 23 setup for erx from erefck 1.5 emac 24 hold for erx from erefck 0 emac 25 setup for erxer from erefck 1.5 emac 26 hold for erxer from erefck 0 emac 27 setup for ecrsdv from erefck 1.5 emac 28 hold for ecrsdv from erefck 0 erefck etxen etx[1:0] erx[1:0] erxer ecrsdv emac 21 emac 22 emac 23 emac 24 emac 25 emac 26 emac 27 emac 28 table 12-27. flash wait states fws read operations maximum operating frequency (mhz) 0 1 cycle 33 1 2 cycles 66
59 32058fs?avr32?08/08 at32uc3a 13. mechanical characteristics 13.1 thermal considerations 13.1.1 thermal data table 13-1 summarizes the thermal resistance data depending on the package. 13.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ? ja = package thermal resistance, junction-to-ambient (c/w), provided in table 13-1 on page 59 . ? jc = package thermal resistance, junction-to-ca se thermal resistance (c/w), provided in table 13-1 on page 59 . ? heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. ?p d = device power consumption (w) estimated from data provided in the section ?power consumption? on page 42 . ?t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a coolin g device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. table 13-1. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air tqfp100 tbd ? c/w jc junction-to-case thermal resistance tqfp100 tbd ja junction-to-ambient thermal resistance still air lqfp144 tbd ? c/w jc junction-to-case thermal resistance lqfp144 tbd t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ =
60 32058fs?avr32?08/08 at32uc3a 13.2 package drawings figure 13-1. tqfp-100 package drawing table 13-2. device and package maximum weight tbd mg table 13-3. package characteristics moisture sensitivity level tbd table 13-4. package reference jedec drawing reference ms-026 jesd97 classification e3
61 32058fs?avr32?08/08 at32uc3a figure 13-2. lqfp-144 package drawing table 13-5. device and package maximum weight tbd mg table 13-6. package characteristics moisture sensitivity level tbd table 13-7. package reference jedec drawing reference ms-026 jesd97 classification e3
62 32058fs?avr32?08/08 at32uc3a 13.3 soldering profile table 13-8 gives the recommended soldering profile from j-std-20. note: it is recommended to apply a soldering temperature higher than 250c. a maximum of three reflow passes is allowed per component. table 13-8. soldering profile profile feature green package average ramp-up rate (217c to peak) tbd preheat temperature 175c 25c tbd temperature maintained above 217c tbd time within 5 ? c of actual peak temperature tbd peak temperature range tbd ramp-down rate tbd time 25 ? c to peak temperature tbd
63 32058fs?avr32?08/08 at32uc3a 14. ordering information 14.1 automotive quality grade the at32uc3a have been developed and manufactured according to the most stringent requirements of the international standard iso-ts -16949. this data sheet will contain limit val- ues extracted from the results of extensive characterization (temperature and voltage). the quality and reliability of the at32uc3a is verified during regular product qualification as per aec-q100 grade 3. as indicated in the ordering information paragraph, the product is available in only one tempera- ture grade t: -40c / + 85c. table 14-1. ordering information device ordering code package conditioning temperature operating range at32uc3a0512 at32uc3a0512-alut 144 lead lqfp tray industrial (-40 ? c to 85 ? c) AT32UC3A0512-ALUR 144 lead lqfp reel industrial (-40 ? c to 85 ? c) at32uc3a0512-altr 144 lead lqfp reel automotive (-40 ? c to 85 ? c) at32uc3a0512-altt 144 lead lqfp tray automotive (-40 ? c to 85 ? c) at32uc3a0512-altes 144 lead lqfp tray automotive (-40 ? c to 85 ? c) samples at32uc3a0256 at32uc3a0256-alut 144 lead lqfp tray industrial (-40 ? c to 85 ? c) at32uc3a0256-alur 144 lead lqfp reel industrial (-40 ? c to 85 ? c) at32uc3a0128 at32uc3a0128-alut 144 lead lqfp tray industrial (-40 ? c to 85 ? c) at32uc3a0128-alur 144 lead lqfp reel industrial (-40 ? c to 85 ? c) at32uc3a1512 at32uc3a1512-aut 100 lead tqfp tray industrial (-40 ? c to 85 ? c) at32uc3a1512-aur 100 lead tqfp reel industrial (-40 ? c to 85 ? c) at32uc3a1256 at32uc3a1256-aut 100 lead tqfp tray industrial (-40 ? c to 85 ? c) at32uc3a1256-aur 100 lead tqfp reel industrial (-40 ? c to 85 ? c) at32uc3a1128 at32uc3a1128-aut 100 lead tqfp tray industrial (-40 ? c to 85 ? c) at32uc3a1128-aur 100 lead tqfp reel industrial (-40 ? c to 85 ? c)
64 32058fs?avr32?08/08 at32uc3a 15. errata all industrial parts labelled with -ues (engineering samples) are revision e parts. 15.1 rev. j 15.1.1 pwm 1. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 3. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 15.1.2 adc 1. sleep mode activation needs additional a to d conversion if the adc sleep mode is activated when the ad c is idle the adc w ill not enter sleep mode before after the next ad conversion. fix/workaround activate the sleep mode in the mode register and then perform an ad conversion. 15.1.3 spi 1. spi slave / pdca tran sfer: no tx underrun flag there is no tx underrun flag available, ther efore in spi slave mode, there is no way to be informed of a character lost in transmission. fix/workaround for pdca transfer: none. 2. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1.
65 32058fs?avr32?08/08 at32uc3a 3. spi bad serial clock generation on 2nd chip_select when scbr = 1, cpol=1 and ncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and cpol=1 and cpha=0, then an aditional pulse will be generated on sck. fix/workaround when multiple cs are in use, if one of the baudrate equals 1, the other must also equal 1 if cpol=1 and cpha=0. 4. spi glitch on rxready flag in slave mode when enabling the spi or during the first transfer in slave mode, the spi can generate a false rxready signal during enabling of the spi or during the first transfer. fix/workaround 1. set slave mode, set required cpol/cpha. 2. enable spi. 3. set the polarity cpol of the line in the opposite value of the required one. 4. set the polarity cpol to the required one. 5. read the rxholding register. transfers can now befin and rxr eady will now behave as expected. 5. spi disable does not work in slave mode fix/workaround read the last received data then perform a software reset. 15.1.4 power manager 1. if the bod level is higher than vddcore, the part is constantly under reset if the bod level is set to a value higher than vddcore and ena bled by fuses, the part will be in constant reset. fix/workaround apply an external voltage on vddcore that is higher than the bod le vel and is lower than vddcore max and disable the bod. 15.1.5 pdca 1. wrong pdca behavior when using tw o pdca channels with the same pid. fix/workaround the same pid should not be assigned to more than one channel. 15.1.6 twi 1. the twi rxrdy flag in sr register is not reset when a software reset is performed. fix/workaround after a software reset, the regi ster twi rhr must be read. 15.1.7 sdramc 1. code execution from external sdram does not work code execution from sdram does not work. fix/workaround do not run code from sdram.
66 32058fs?avr32?08/08 at32uc3a 15.1.8 processor and architecture 1. ldm instruction with pc in the regist er list and without ++ increments rp for ldm with pc in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is alwa ys updated. this happens even if the ++ field is cleared. specifically, the increment of the pointer is done in parallel with the testing of r12. fix/workaround none. 2. rete instruction does not clear sreg[l] from interrupts. the rete instruction clears sreg[l] as expected from exceptions. fix/workaround when using the stcond instruct ion, clear sreg[l] in the stacked value of sr before returning from interrupts with rete.
67 32058fs?avr32?08/08 at32uc3a 15.2 rev. i 15.2.1 pwm 1. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 3. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 15.2.2 adc 1. sleep mode activation needs additional a to d conversion if the adc sleep mode is activated when the ad c is idle the adc w ill not enter sleep mode before after the next ad conversion. fix/workaround activate the sleep mode in the mode register and then perform an ad conversion. 15.2.3 spi 1. spi slave / pdca tran sfer: no tx underrun flag there is no tx underrun flag available, ther efore in spi slave mode, there is no way to be informed of a character lost in transmission. fix/workaround for pdca transfer: none. 2. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1. 3. spi bad serial clock generation on 2nd chip_select when scbr = 1, cpol=1 and ncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and cpol=1 and cpha=0, then an aditional pulse will be generated on sck. fix/workaround
68 32058fs?avr32?08/08 at32uc3a when multiple cs are in use, if one of the baudrate equals 1, the other must also equal 1 if cpol=1 and cpha=0. 4. spi glitch on rxready flag in slave mode when enabling the spi or during the first transfer in slave mode, the spi can generate a false rxready signal during enabling of the spi or during the first transfer. fix/workaround 1. set slave mode, set required cpol/cpha. 2. enable spi. 3. set the polarity cpol of the line in the opposite value of the required one. 4. set the polarity cpol to the required one. 5. read the rxholding register. transfers can now befin and rxr eady will now behave as expected. 5. spi disable does not work in slave mode fix/workaround read the last received data then perform a software reset. 15.2.4 power manager 1. if the bod level is higher than vddcore, the part is constantly under reset if the bod level is set to a value higher than vddcore and ena bled by fuses, the part will be in constant reset. fix/workaround apply an external voltage on vddcore that is higher than the bod le vel and is lower than vddcore max and disable the bod. 15.2.5 flashc 1. on at32uc3a0512 and at32uc3a1512, corrupted read in flash after flashc wp, ep, ea, wup, eup commands may happen - after a flashc write page (wp) or erase page (ep) command applied to a page in a given half of the flash (first or last 256 kb of flash), reading (data read or code fetch) the other half of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc erase all (ea) command, reading (data read or code fetch) the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc write user page (wup) or erase user page (eup) command, reading (data read or code fetch) the second half (last 256 kb) of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. fix/workaround flashc wp, ep, ea, wup, eup commands: these commands must be issued from ram or through the ebi. after these commands, read twice one flash page initialized to 00h in each half part of the flash. 15.2.6 pdca 1. wrong pdca behavior when using tw o pdca channels with the same pid.
69 32058fs?avr32?08/08 at32uc3a workaround/fix the same pid should not be assigned to more than one channel. 15.2.7 gpio 1. some gpio vih (input high voltage) are 3.6v max instead of 5v tolerant only 11 gpios remain 5v tolerant (vihmax=5v): pb01, pb02, pb03, pb10, pb19, pb20, pb21, pb22, pb23, pb27, pb28 . workaround/fix none. 15.2.8 twi 1. the twi rxrdy flag in sr register is not reset when a software reset is performed. fix/workaround after a software reset, the regi ster twi rhr must be read. 15.2.9 sdramc 1. code execution from external sdram does not work code execution from sdram does not work. fix/workaround do not run code from sdram. 15.2.10 processor and architecture 1. ldm instruction with pc in the regist er list and without ++ increments rp for ldm with pc in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is alwa ys updated. this happens even if the ++ field is cleared. specifically, the increment of the pointer is done in parallel with the testing of r12. fix/workaround none. 2. rete instruction does not clear sreg[l] from interrupts. the rete instruction clears sreg[l] as expected from exceptions. fix/workaround when using the stcond instruct ion, clear sreg[l] in the stacked value of sr before returning from interrupts with rete.
70 32058fs?avr32?08/08 at32uc3a 15.3 rev. h 15.3.1 pwm 1. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 3. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 15.3.2 adc 1. sleep mode activation needs additional a to d conversion if the adc sleep mode is activated when the ad c is idle the adc w ill not enter sleep mode before after the next ad conversion. fix/workaround activate the sleep mode in the mode register and then perform an ad conversion. 15.3.3 spi 1. spi slave / pdca tran sfer: no tx underrun flag there is no tx underrun flag available, ther efore in spi slave mode, there is no way to be informed of a character lost in transmission. fix/workaround for pdca transfer: none. 2. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1 3. spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset.
71 32058fs?avr32?08/08 at32uc3a 4. spi bad serial clock generation on 2nd chip_select when scbr = 1, cpol=1 and ncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and cpol=1 and cpha=0, then an aditional pulse will be generated on sck. fix/workaround when multiple cs are in use, if one of the baudrate equals 1, the other must also equal 1 if cpol=1 and cpha=0. 5. spi glitch on rxready flag in slave mode when enabling the spi or during the first transfer in slave mode, the spi can generate a false rxready signal during enabling of the spi or during the first transfer. fix/workaround 1. set slave mode, set required cpol/cpha. 2. enable spi. 3. set the polarity cpol of the line in the opposite value of the required one. 4. set the polarity cpol to the required one. 5. read the rxholding register. transfers can now befin and rxr eady will now behave as expected. 6. spi disable does not work in slave mode fix/workaround read the last received data then perform a software reset. 15.3.4 power manager 1. wrong reset causes when bod is activated setting the bod enable fuse will cause the rese t cause register to list bod reset as the reset source even though the part was reset by another source. fix/workaround do not set the bod enable fuse, but activate the bod as soon as your program starts. 2. if the bod level is higher than vddcore, the part is constantly under reset if the bod level is set to a value higher than vddcore and ena bled by fuses, the part will be in constant reset. fix/workaround apply an external voltage on vddcore that is higher than the bod le vel and is lower than vddcore max and disable the bod. 15.3.5 flashc 1. on at32uc3a0512 and at32uc3a1512, corrupted read in flash after flashc wp, ep, ea, wup, eup commands may happen - after a flashc write page (wp) or erase page (ep) command applied to a page in a given half of the flash (first or last 256 kb of flash), reading (data read or code fetch) the other half of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc erase all (ea) command, reading (data read or code fetch) the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc write user page (wup) or erase user page (eup) command, reading
72 32058fs?avr32?08/08 at32uc3a (data read or code fetch) the second half (last 256 kb) of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. fix/workaround flashc wp, ep, ea, wup, eup commands: these commands must be issued from ram or through the ebi. after these commands, read twice one flash page initialized to 00h in each half part of the flash. 15.3.6 pdca 1. wrong pdca behavior when using tw o pdca channels with the same pid. workaround/fix the same pid should not be assigned to more than one channel. 15.3.7 twi 1. the twi rxrdy flag in sr register is not reset when a software reset is performed. fix/workaround after a software reset, the regi ster twi rhr must be read. 15.3.8 sdramc 1. code execution from external sdram does not work code execution from sdram does not work. fix/workaround do not run code from sdram. 15.3.9 processor and architecture 1. ldm instruction with pc in the regist er list and without ++ increments rp for ldm with pc in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is alwa ys updated. this happens even if the ++ field is cleared. specifically, the increment of the pointer is done in parallel with the testing of r12. fix/workaround none. 2. rete instruction does not clear sreg[l] from interrupts. the rete instruction clears sreg[l] as expected from exceptions. fix/workaround when using the stcond instruct ion, clear sreg[l] in the stacked value of sr before returning from interrupts with rete.
73 32058fs?avr32?08/08 at32uc3a 15.4 rev. e 15.4.1 spi 1. spi fdiv option does not work selecting clock signal using fdiv = 1 does not work as specified. fix/workaround do not set fdiv = 1. 2. spi slave / pdca tran sfer: no tx underrun flag there is no tx underrun flag available, ther efore in spi slave mode, there is no way to be informed of a character lost in transmission. fix/workaround for pdca transfer: none. 3. spi bad serial clock generation on 2nd chip select when scbr=1, cpol=1 and cncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn?t equal to 1, and cpol =1 and cpha=0, then an addi tional pulse will be generated on sck. fix/workaround when multiple cs are in use, if one of the baudrate equals to 1, the other must also equal 1 if cpol=1 and cpha=0. 4. spi glitch on rxready flag in slave mode when enabling the spi or during the first transfer in slave mode, the spi can generate a false rxready signal during enabling of the spi or during the first transfer. fix/workaround 1. set slave mode, set required cpol/cpha. 2. enable spi. 3. set the polarity cpol of the line in the opposite value of the required one. 4. set the polarity cpol to the required one. 5. read the rxholding register. transfers can now befin and rxr eady will now behave as expected. 5. spi csnaat bit 2 in register csr0...csr3 is not available. fix/workaround do not use this bit. 6. spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset. 7. spi bad serial clock generation on 2nd chip_select when scbr = 1, cpol=1 and ncpha=0 when multiple cs are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and cpol=1 and cpha=0, then an aditional pulse will be generated on sck.
74 32058fs?avr32?08/08 at32uc3a fix/workaround when multiple cs are in use, if one of the baudrate equals 1, the other must also equal 1 if cpol=1 and cpha=0. 15.4.2 pwm 1. pwm counter restarts at 0x0001 the pwm counter restarts at 0x0001 and not 0x0000 as specified. because of this the first pwm period has one more clock cycle. fix/workaround - the first period is 0x0000, 0x0001, ..., period - consecutive periods are 0x0001, 0x0002, ..., period 2. pwm channel interrupt enabling triggers an interrupt when enabling a pwm channel that is configured with center aligned period (calg=1), an interrupt is signalled. fix/workaround when using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 3. pwm update period to a 0 value does not work it is impossible to update a period equal to 0 by the using the pwm update register (pwm_cupd). fix/workaround do not update the pwm_cupd register with a value equal to 0. 4. pwm channel status may be wrong if disabled before a period has elapsed before a pwm period has elapsed, the read channel status may be wrong. the chidx-bit for a pwm channel in the pwm enable register will read '1' fo r one full pwm period even if the channel was disabled before the period elapsed. it will then read '0' as expected. fix/workaround reading the pwm channel status of a disabled channel is only correct after a pwm period has elapsed. 15.4.3 ssc 1. ssc does not trigger rf when data is low the ssc cannot transmit or receive data wh en cks = ckdiv and cko = none, in tcmr or rcmr respectively. fix/workaround set cko to a value that is not "none" and bypass the output of the tk/rk pin with the pio. 2. ssc data is not sent unless clock is set as output the ssc cannot transmit or receive data wh en cks = ckdiv and cko = none, in tcmr or rcmr respectively. fix/workaround set cko to a value that is not "none" and bypass the output of the tk/rk pin with the pio.
75 32058fs?avr32?08/08 at32uc3a 15.4.4 usb 1. usb no end of host reset signaled upon disconnection in host mode, in case of an unexpected devic e disconnection whereas a usb reset is being sent by the usb controller, the uhcon.reset bi t may not been clear ed by the hardware at the end of the reset. fix/workaround a software workaround consists in testing (by polling or interrupt ) the disconnection (uhint.ddisci == 1) while waiting for the end of reset (uhcon.reset == 0) to avoid being stuck. 2. usbfsm and uhaddr1/2/3 re gisters are no t available. do not use usbfsm register. fix/workaround do not use usbfsm register and use hcon[6:0] field instead for all the pipes. 15.4.5 processor and architecture 1. incorrect processor id the processor id reads 0x01 and not 0x02 as it should. fix/workaround none. 2. bus error should be masked in debug mode if a bus error occurs during debug mode, the processor will not respond to debug com- mands through the dinst register. fix/workaround a reset of the device will make the cp u respond to debug commands again. 3. read modify write (rmw) instructions on data outside the internal ram does not work. read modify write (rmw) instructions on da ta outside the internal ram does not work. fix/workaround do not perform rmw instructions on data outside the internal ram. 4. crc calculation of a locked device will calculate crc for 512 kb of flash memory, even though the part has less flash. fix/workaround the flash address space is wrap ping, so it is possible to use the crc value by calculating crc of the flash content concatenated with itself n times. where n is 512 kb/flash size. 5. need two nops instruction after instructions masking interrupts the instructions following in the pipeline the instruction masking the interrupt through sr may behave abnormally. fix/workaround place two nops instructions after each ssrf or mtsr instruction setting ixm or gm in sr.
76 32058fs?avr32?08/08 at32uc3a 6. cpu cycle counter does not reset the count system register on compare match. the device revision e does not reset the co unt system register on compare match. in this revision, the count register is clocke d by the cpu clock, so when the cpu clock stops, so does incrementing of count . fix/workaround none. 7. memory protection unit (mpu) is non functional. fix/workaround do not use the mpu. 8. the following alternate gpio func tion c are not available in reve macb-wol on gpio9 (pa09), macb-wol on gpio18 (pa18), usb-usb_id on gpio21 (pa21), usb-usb_vbof on gpio22 (pa22), and all function b and c on gpio70 to gpio101 (px00 to px39). fix/workaround do not use these alternate b and c functions on the listed gpio pins. 9. clock connection table on rev e here is the table of rev e figure 15-1. timer/counter clock connections on reve 10. local bus fast gpio not available in reve. fix/workaround do not use on this silicon revision. 11. spurious interrupt may corrupt core sr mode to exception if the rules listed in the chapter `masking inte rrupt requests in peripheral modules' of the avr32uc technical reference manual are not followed, a spurious interrupt may occur. an interrupt context will be pushed onto the stac k while the core sr mode will indicate an exception. a rete instruction would then corrupt the stack.. fix/workaround follow the rules of the avr32uc technical reference manual. to increase software robustness, if an exception mode is detec ted at the beginning of an interrupt handler, change the stack interrupt context to an e xception context and issue a rete instruction. source name connection internal timer_clock1 32 khz oscillator timer_clock2 pba clock / 4 timer_clock3 pba clock / 8 timer_clock4 pba clock / 16 timer_clock5 pba clock / 32 external xc0 xc1 xc2
77 32058fs?avr32?08/08 at32uc3a 12. cpu cannot operate on a divided slow clock (internal rc oscillator) fix/workaround do not run the cpu on a divided slow clock. 15.4.6 sdramc 1. code execution from external sdram does not work code execution from sdram does not work. fix/workaround do not run code from sdram. 2. sdram sdcke rise at the same time as sdck while exiti ng self-refresh mode sdcke rise at the same time as s dck while exiting self-refresh mode. fix/workaround none. 15.4.7 usart 1. usart manchester encoder not working manchester encoding/decoding is not working. fix/workaround do not use manchester encoding. 2. usart rxbreak problem when no timeguard in asynchronous mode the rxbreak flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. fix/workaround if the nbstop is 1, timeguard should be different from 0. 3. usart handshaking: 2 characters sent / cts rises when tx if cts switches from 0 to 1 during the tx of a character, if the holding register is not empty, the txholding is also transmitted. fix/workaround none. 4. usart pdc and timeguard not supported in manchester manchester encoding/decoding is not working. fix/workaround do not use manchester encoding. 5. usart spi mode is non functional on this revision. fix/workaround do not use the usart spi mode. 6. dcd is active high instead of low. in modem mode the dcd signal is assumed to be active high by the usart, butshould have been active low. fix/workaround
78 32058fs?avr32?08/08 at32uc3a add an external inverter to the dcd line. 15.4.8 power manager 1. voltage regulator input and output is connected to vddio and vddcore inside the device the voltage regulator input and output is connected to vddio and vddcore respectively inside the device. fix/workaround do not supply vddcore externally, as this s upply will work in paralell with the regulator. 2. wrong reset causes when bod is activated setting the bod enable fuse will cause the rese t cause register to list bod reset as the reset source even though the part was reset by another source. fix/workaround do not set the bod enable fuse, but activate the bod as soon as your program starts. 3. pll0/1 lock control does not work lock control does not work for pll0 and pll1. fix/workaround in pll0/1 control register, the bit 7 should be set in order to prevent unexpected behaviour. 4. peripheral bus a maximum frequency is 33mhz instead of 66mhz. fix/workaround do not set pba frequency higher than 33 mhz. 5. pcx pins go low in stop mode in sleep mode stop all pcx pi ns will be controlled by gpio module instead of oscillators. this can cause drive contention on the xinx in worst case. fix/workaround before entering stop mode set all pcx pins to input and gpio controlled. 6. on some rare parts, the maximum hsb and cpu speed is 50mhz instead of 66mhz. fix/workaround do not set the hsb/cpu speed higher than 50mhz when the firmware generate exceptions. 7. if the bod level is higher than vddcore, the part is constantly under reset if the bod level is set to a value higher than vddcore and ena bled by fuses, the part will be in constant reset. fix/workaround apply an external voltage on vddcore that is higher than the bod le vel and is lower than vddcore max and disable the bod. 8. system timer mask (bit 16) of the pm cpumask register is not available. fix/workaround do not use this bit.
79 32058fs?avr32?08/08 at32uc3a 15.4.9 hmatrix 1. hmatrix fixed priority arbitration does not work fixed priority arbitration does not work. fix/workaround use round-robin arbitration instead. 15.4.10 adc 1. adc possible miss on drdy when disabling a channel the adc does not work properly when more than one channel is enabled. fix/workaround do not use the adc with more than one channel enabled at a time. 2. adc ovre flag sometimes not reset on status register read the ovre flag does not clear properly if read simultaneously to an end of conversion. fix/workaround none. 3. sleep mode activation needs additional a to d conversion if the adc sleep mode is activated when the ad c is idle the adc w ill not enter sleep mode before after the next ad conversion. fix/workaround activate the sleep mode in the mode register and then perform an ad conversion. 15.4.11 abdac 1. audio bitstream dac is not functional. fix/workaround do not use the abdac on reve. 15.4.12 flashc 1. the address of flash general purpose fuse register low (fgpfrlo) is 0xfffe140c on reve instead of 0xfffe1410. fix/workaround none. 2. the command quick page read user page(qprup) is not functional. fix/workaround none. 3. pagen semantic field for program gp fuse byte is writedata[7:0], byteaddress[1:0] on revision e instead of writedata[7:0], byteaddress[2:0]. fix/workaround none. 4. on at32uc3a0512 and at32uc3a1512, corrupted read in flash after flashc wp, ep, ea, wup, eup commands may happen
80 32058fs?avr32?08/08 at32uc3a - after a flashc write page (wp) or erase page (ep) command applied to a page in a given half of the flash (first or last 256 kb of flash), reading (data read or code fetch) the other half of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc erase all (ea) command, reading (data read or code fetch) the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. - after a flashc write user page (wup) or erase user page (eup) command, reading (data read or code fetch) the second half (last 256 kb) of the flash may fail. this may lead to an exception or to other errors derived from this corrupted read access. fix/workaround flashc wp, ep, ea, wup, eup commands: these commands must be issued from ram or through the ebi. after these commands, read twice one flash page initialized to 00h in each half part of the flash. 15.4.13 rtc 1. writes to control (ctrl), top (top) and value (val) in the rtc are discarded if the rtc peripheral bus clock (pba) is divided by a factor of four or more relative to the hsb clock. fix/workaround do not write to the rtc registers using the pe ripheral bus clock (pba) divided by a factor of four or more relative to the hsb clock. 2. the rtc clken bit (bit number 16) of ctrl register is not available. fix/workaround do not use the clken bit of the rtc on rev e . 15.4.14 ocd 1. stalled memory access instruction writeback fails if followed by a hw breakpoint. consider the following assembly code sequence: a b if a hardware breakpoint is placed on instruction b, and instruction a is a memory access instruction, register file updates from instruction a can be discarded. fix/workaround do not place hardware breakpoints, use software breakpoints instead. alternatively, place a hardware breakpoint on the instruction before the memory access instruction and then single step over the memory access instruction. 15.4.15 pdca 1. wrong pdca behavior when using tw o pdca channels with the same pid. workaround/fix the same pid should not be assigned to more than one channel. 15.4.16 twi 1. the twi rxrdy flag in sr register is not reset when a software reset is performed. fix/workaround after a software reset, the regi ster twi rhr must be read. 15.4.17 processor and architecture 1. ldm instruction with pc in the regist er list and without ++ increments rp
81 32058fs?avr32?08/08 at32uc3a for ldm with pc in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is alwa ys updated. this happens even if the ++ field is cleared. specifically, the increment of the pointer is done in parallel with the testing of r12. fix/workaround none. 2. rete instruction does not clear sreg[l] from interrupts. the rete instruction clears sreg[l] as expected from exceptions. fix/workaround when using the stcond instruct ion, clear sreg[l] in the stacked value of sr before returning from interrupts with rete.
82 32058fs?avr32?08/08 at32uc3a 16. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 16.1 rev. f ? 08/08 16.2 rev. e ? 04/08 16.3 rev. d ? 04/08 16.4 rev. c ? 10/07 16.5 rev. b ? 10/07 1. add revision j to ?errata? on page 64 . 2. update dmips number in ?features? on page 1 . 1. open drain mode removed from ?general-purpose input/output controller (gpio)? on page 151 . 1. updated ?signal description list? on page 8 . removed rxdn and txdn from usart section. 2. updated ?errata? on page 64 . rev g replaced by rev h. 1. updated ?signal description list? on page 8 . removed rxdn and txdn from usart section. 2. updated ?errata? on page 64 . rev g replaced by rev h. 1. updated ?features? on page 1 . 2. update ?blockdiagram? on page 4 with local bus. 3. updated ?peripherals? on page 34 with local bus. 4. add spi feature in ?universial synchronous/asynchronous receiver/transmitter (usart)? on page 315 .
83 32058fs?avr32?08/08 at32uc3a 16.6 rev. a ? 03/07 5. updated ?usb on-the-go interface (usbb)? on page 517 . 6. updated ?jtag and boundary scan? on page 750 with programming procedure . 7. add description fo r silicon rev g. 1. initial revision.
i 32058fs?avr32?08/08 at32uc3a table of contents 1 description ............ .............. .............. ............... .............. .............. ............ 3 2 configuration summary ........ .............. .............. .............. .............. .......... 4 3 abbreviations ........... ................ ................ ................. ................ ............... 4 4 blockdiagram ............. ................ ................. ................ ................. ............ 5 4.1processor and architecture .......................................................................................6 5 signals description ............ .............. ............... .............. .............. ............ 8 6 package and pinout ................. ................ ................. ................ ............. 13 7 power considerations ........ .............. ............... .............. .............. .......... 16 7.1power supplies .......................................................................................................16 7.2voltage regulator ....................................................................................................17 7.3analog-to-digital converter (a.d.c) reference. .......................................................18 8 i/o line considerations ...... .............. ............... .............. .............. .......... 19 8.1jtag pins ................................................................................................................19 8.2reset_n pin ............ ................. ................ ................ ................ ................ .............19 8.3twi pins ..................................................................................................................1 9 8.4gpio pins ................................................................................................................19 9 memories ............... .............. .............. ............... .............. .............. .......... 20 9.1embedded memories ..............................................................................................20 9.2physical memory map .............................................................................................20 9.3bus matrix connections ..........................................................................................21 10 peripherals ............ .............. .............. ............... .............. .............. .......... 23 10.1peripheral address map ........................................................................................23 10.2cpu local bus mapping .......................................................................................24 10.3interrupt request signal map ................................................................................26 10.4clock connections ................................................................................................28 10.5nexus ocd aux port connections .......................................................................29 10.6pdc handshake signals ........................................................................................29 10.7peripheral multiplexing on i/o lines .......................................................................30 10.8oscillator pinout ....................................................................................................33 10.9usart configuration ............................................................................................33 10.10gpio ...................................................................................................................34
10.11peripheral overview .............................................................................................34 11 boot sequence ........... ................ ................. ................ ................. .......... 38 11.1starting of clocks ...................................................................................................38 11.2fetching of initial instructions ................................................................................38 12 electrical characteristics ... .............. ............... .............. .............. .......... 39 12.1absolute maximum ratings* .................................................................................39 12.2dc characteristics ................................................................................................40 12.3regulator characteristics .......................................................................................41 12.4analog characteristics ...........................................................................................41 12.5power consumption ..............................................................................................42 12.6clock characteristics .............................................................................................44 12.7crystal oscillator characteristis ............................................................................44 12.8adc characteristics ..............................................................................................46 12.9ebi timings ...........................................................................................................47 12.10jtag timings ......................................................................................................53 12.11spi characteristics ..............................................................................................54 12.12macb characteristics .........................................................................................56 12.13flash characteristics ...........................................................................................58 13 mechanical characteristics ..... ................ ................. ................ ............. 59 13.1thermal considerations ........................................................................................59 13.2package drawings ................................................................................................60 13.3soldering profile ....................................................................................................62 14 ordering information .......... .............. ............... .............. .............. .......... 63 14.1automotive quality grade .....................................................................................63 15 errata ............. ................ ................. ................ ................. .............. .......... 64 15.1rev. j .................................................................................................................... 64 15.2rev. i .................................................................................................................... .67 15.3rev. h ...................................................................................................................7 0 15.4rev. e .................................................................................................................... 73 16 datasheet revision history .. .............. .............. .............. .............. ........ 82 16.1rev. f ? 08/08 .......................................................................................................82 16.2rev. e ? 04/08 .......................................................................................................82 16.3rev. d ? 04/08 ......................................................................................................82 16.4rev. c ? 10/07 ......................................................................................................82
32058fs?avr32?08/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr32@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, avr ? and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. 16.5rev. b ? 10/07 .......................................................................................................82 16.6rev. a ? 03/07 .......................................................................................................83

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